Modular sequential logic Use latches, flip-flops and combinational logic –Flip-flops usually grouped to form a register Shift registers –n bits {x n …x 1 } –In this master-slave, each FF is a “cell” –On control pulse, 0  1 M i gets S i+1 –On control pulse, 1  0 S i gets M i

Shift registers Edge-triggered SR flip-flop example –This one contains negative edge triggered FFs Generic shift register:

Shift registers Generic shift registers –Parallel in, serial out Serial in, parallel out

Generic shift registers

Standard TTL shift registers

74164: 8-bit, serial in, serial/parallel out

Standard TTL shift registers operation

Standard TTL shift registers 74194: 4 bit, bidirectional, serial-in, serial/parallel out shift register –Asynchronous common clear –Synchronous load

Standard TTL shift registers –74194: 4 bit, bidirection al, serial- in, serial/para llel out shift register 74194

74194 operation Internal clock CK = CLOCK + S0’S1’ –When S0 and S1 are both 0, CK = 1; hold Set input of internal FF (e.g. B) is S B = Q CS0’ + Q AS1’ + BS0S1 –S1=1 & S0=0  S B = Q C ; shift left –S1=0 & S0=1  S B = Q A ; shift right –S1=1 & S0=1  S B = B; external load –Synchronous parallel load

Serial adder Data words X and Y loaded in parallel into shift registers, shifted out and added by one 1-bit full adder; result Z=X+Y shifted into register Sequence: –Clear –Preset –Shift

Accumulators Serial accumulator: –Clear Z & carry –Load X –Do n shifts/adds –Load again etc… Z carry X

Accumulators Parallel accumulator: –Which design has a longer delay to add? Serial or parallel?