EE5342 – Semiconductor Device Modeling and Characterization Lecture 23 April 12, 2010 Professor Ronald L. Carter

L23 04/12/102 n-channel enhancement MOSFET in ohmic region 0< V T < V G V B < 0 E Ox,x > 0 Acceptors Depl Reg V S = 0 0< V D < V DS,sat e - e - e - e - e - n+ p-substrate Channel

L23 04/12/103 Conductance of inverted channel Q’ n = - C’ Ox (V GC -V T ) n’ s = C’ Ox (V GC -V T )/q, (# inv elect/cm 2 ) The conductivity  n = (n’ s /t) q  n G =  n (Wt/L) = n’ s q  n (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’ s q  n W)

L23 04/12/104 Basic I-V relation for MOS channel

L23 04/12/105 I-V relation for n-MOS (ohmic reg) IDID V DS V DS,sat I D,sat ohmic non-physical saturated

L23 04/12/106 Universal drain characteristic 9I D1 IDID 4I D1 I D1 V GS =V T +1V V GS =V T +2V V GS =V T +3V V DS saturated, V DS >V GS -V T ohmic

L23 04/12/107 Characterizing the n-ch MOSFET VDVD IDID D S G B V GS VTVT

L23 04/12/108 Low field ohmic characteristics

L23 04/12/109 MOSFET Device Structre Fig. 4-1, M&A*

L23 04/12/ a (A&M)

L23 04/12/1011 Figure 4-7b (A&M)

L23 04/12/1012 Figure 4-8a (A&M)

L23 04/12/1013 Figure 4-8b (A&M)

L23 04/12/1014 Body effect data Fig 9.9**

L23 04/12/1015 MOSFET equivalent circuit elements Fig 10.51*

L23 04/12/1016 n-channel enh. circuit model G D B S C gs C gd C gb C bs C bd RD RG RB RDS Idrain D SS D SD

L23 04/12/1017 MOS small-signal equivalent circuit Fig 10.52*

L23 04/12/1018 MOSFET circuit parameters

L23 04/12/1019 MOSFET circuit parameters (cont)

L23 04/12/1020 Substrate bias effect on V T (body-effect)

L23 04/12/1021 Body effect data Fig 9.9**

L23 04/12/1022 Fully biased n- channel V T calc

L23 04/12/1023 Values for  ms with silicon gate

L23 04/12/1024 Q’ d,max and x d,max for biased MOS capacitor Fig 8.11** x d,max (microns) |Q’ d,max |/q (cm -2 )

L23 04/12/1025 I-V relation for n-MOS IDID V DS V DS,sat I D,sat ohmic non-physical saturated

L23 04/12/1026 MOS channel- length modulation Fig 11.5*

L23 04/12/1027 Analysis of channel length modulation

L23 04/12/1028 Channel length mod- ulated drain char Fig 11.6*

L23 04/12/1029 Associating the output conductance IDID V DS V DS,sat I D,sat

L23 04/12/1030 SPICE mosfet Model Instance CARM*, Ch. 4, p. 290 L = Ch. L. [m] W = Ch. W. [m] AD = Drain A [m 2 ] AS = Source A[m 2 ] NRD, NRS = D and S diff in squares M = device multiplier

L23 04/12/1031 SPICE mosfet model levels Level 1 is the Schichman-Hodges model Level 2 is a geometry-based, analytical model Level 3 is a semi-empirical, short- channel model Level 4 is the BSIM1 model Level 5 is the BSIM2 model, etc.

L23 04/12/1032 SPICE Parameters Level (Static)

L23 04/12/1033 SPICE Parameters Level (Static) * 0 = aluminum gate, 1 = silicon gate opposite substrate type, -1 = silicon gate same as substrate.

L23 04/12/1034 SPICE Parameters Level (Q & N)

L23 04/12/1035 References CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, **M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, *Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997