ECE 331 – Digital System Design Introduction to Sequential Circuits and Latches (Lecture #16)

ECE Digital System Design2 Sequential Logic Circuits

ECE Digital System Design3 Sequential Logic Circuits Combinational Logic Circuits  Output is a function of the inputs only.  Do not have “history” Sequential Logic Circuits  Output is a function of the inputs and the present state.  Have “history”  Maintain state information  Require memory elements

ECE Digital System Design4 Sequential Logic Circuits

ECE Digital System Design5 Basic Memory Elements

ECE Digital System Design6 Basic Memory Elements Latch  Clock input is level sensitive.  Output can change multiple times during a clock cycle.  Output changes while clock is active. Flip Flop  Clock input is edge sensitive.  Output can change only once during a clock cycle.  Output changes on clock transition.

ECE Digital System Design7 Basic Memory Elements Both latches and flip flops use feedback to achieve “memory”.

ECE Digital System Design8 A Simple Memory Element AB (what is the problem with this circuit?)

ECE Digital System Design9 SR Latch (NOR gate implementation)

ECE Digital System Design10 SR Latch Q a Q b R S SRQ a Q b /1 1/ (no change) Characteristic table

ECE Digital System Design11 Resetting the SR Latch (Qa = 0) SR Latch

ECE Digital System Design12 SR Latch: S = 0, R = 1 R = 1 → Qa = 0 S = 0 & Qa = 0 → Qb = 1 Latch is reset. Time R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 0, R = 1 Qa = 0 Qb = 1

ECE Digital System Design13 Setting the SR Latch (Qa = 1) SR Latch

ECE Digital System Design14 SR Latch: S = 1, R = 0 S = 1 → Qb = 0 R = 0 & Qb = 0 → Qa = 1 Latch is set. Time R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 1, R = 0 Qa = 1 Qb = 0

ECE Digital System Design15 Storing the value in the SR Latch (Qa + = Qa) SR Latch

ECE Digital System Design16 SR Latch: S = 0, R = 0; Qa = 0 S = 0 & Qa = 0 → Qb = 1 R = 0 & Qb = 1 → Qa = 0 Behavior of latch is consistent. Time R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 0, R = 0 Qa = 0Qb = 1 Qa = 0 Latch stores the value of Qa

ECE Digital System Design17 SR Latch: S = 0, R = 0; Qa = 1 S = 0 & Qa = 1 → Qb = 0 R = 0 & Qb = 0 → Qa = 1 Behavior of latch is consistent. Time R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 0, R = 0 Qa = 1 Qb = 0 Qa = 1 Latch stores the value of Qa

ECE Digital System Design18 The undefined state of the SR Latch (Qa = Qb = 0) SR Latch

ECE Digital System Design19 SR Latch: S = 1, R = 1 S = 1 → Qb = 0; R = 1 → Qa = 0 Time R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 1, R = 1 Qa = 0 Qb = 0

ECE Digital System Design20 SR Latch: S = 1, R = 1 S = 1 → Qb = 0; R = 1 → Qa = 0 Time R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 1, R = 1 Qa = 0 Qb = 0

ECE Digital System Design21 SR Latch: The undefined state What if both S and R transition from 1 to 0 at the same time? (S = 1 → 0 & R = 1 → 0)

ECE Digital System Design22 SR Latch: The undefined state If S and R both transition to 0 simultaneously,  Output is unpredictable  Dependent on speed of the 2 NOR gates. Time R S Q a Q b ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 S = 1 → 0 R = 1 → 0 Qa = ? Qb = ?

ECE Digital System Design23 SR Latch: The undefined state If the top NOR gate is faster,  then R = 0 & Qb = 0 → Qa = 1  and then S = 0 & Qa = 1 → Qb = 0.  Stores Qa = 1, Qb = 0 (set). Q a Q b R S

ECE Digital System Design24 SR Latch: The undefined state If the bottom NOR gate is faster,  then S = 0 & Qa = 0 → Qb = 1  and then R = 0 & Qb = 1 → Qa = 0.  Stores Qa = 0, Qb = 1 (reset). Q a Q b R S

ECE Digital System Design25 Gated SR Latch (NOR gate implementation)

ECE Digital System Design26 Gated SR Latch R1R1 S1S1 undefined set reset store

ECE Digital System Design27 Gated SR Latch

ECE Digital System Design28 Gated SR Latch: State Equation State Equation: Q + = S + R'.Q  Q is the present (or current) state.  Q + is the next state. After the transition of the output Q.  The next state is a function of the inputs and the present state. Inputs: S and R Present State: Q  Note: Q is also denoted as Q(t)  and Q + is also denoted as Q(t+1).

ECE Digital System Design29 Gated SR Latch (NAND gate implementation)

ECE Digital System Design30 Gated SR Latch S R Clk Q Q R' S' undefined set reset store Characteristic table SRS'R'Q(t+1)Q'(t+1) Q(t)Q'(t)

ECE Digital System Design31 Gated D Latch

ECE Digital System Design32 Gated D Latch R' S' set reset store

ECE Digital System Design33 Gated D Latch: Clk = 0 Clk = 0 Clk = 0 → S' = R' = 1 S' = R' = 1 → Q + = Q  Next state = present state Latch stores the value of Q

ECE Digital System Design34 Gated D Latch: Clk = 1 Clk = 1 Clk = 1 → S' = D', R' = D S' = D', R' = D → Q + = D  Next state = input Output (Q) follows the input (D)

ECE Digital System Design35 Gated D Latch State Equation: Q + = D  Q + is the next state  D is the input Eliminates the unstable case  S' = R' = 0 cannot occur.  The values of S' and R' are always complementary when the clock is high (active).

ECE Digital System Design36 Gated D Latch: Issues Must satisfy setup and hold times.  Otherwise, the output will be unpredictable or metastable. Glitches on D are passed to Q when clock is high.  Use edge-triggered or Master-Slave D Flip-Flop to overcome this undesirable behavior. t su t h Clk D Q

ECE Digital System Design37 Acknowledgments The slides used in this lecture were taken, with permission, from those provided by McGraw-Hill for Fundamentals of Digital Logic with VHDL Design (3 rd Edition). They are the property of and are copyrighted by McGraw-Hill Higher Education.