“TALK board status” R.Fantechi, G.Lamanna & D.Gigi (CERN)

TAXI chip test TAXI TTC original TALKDrive the TAXI chip with the TTC information is the original purpose of the TALK board (many functionalies has been added) TELL1 TAXITELL1 firmware prepared to send information through the TAXI PP SL TTC TAXI TALK FPGA To CPD to R/O PC

TAXI chip test

NA48 TSData format equal to the one used in NA48 TS FSMPP TAXIFSM in PP to prepare data for the TAXI 10 MHz TAXIPPAsynchronous transmission: not phase locked between 10 MHz for TAXI and PP ByteContents #1Event number (7-0) #2Event number (15-8) #3Event type (7-0) #4Event type (15-8) #5Time Stamp (7-0) #6Time Stamp (15-8) #7Time Stamp (23-16) #8Error Time Stamp (29-4)

TAXI chip test

TAXISimple TAXI Receiver board “handmade” to decode the serial stream PECLThe serial transmission is done with a PECL pair 10 MHz TAXIPhase random 10 MHz clock wrt to the TAXI sender TAXILogic State Analyzer to debug the TAXI decoded output TAXI perfectlyThe TAXI works perfectly! clock PECL TAXI receiver

TALK controller TALK tdspydaemon mode TELxxdirect ethernet TALKThe TALK controller exploits the communication socket available using tdspy in daemon mode, to send commands to the TELxx and the direct ethernet connection to sendo command to the TALK

TALK Controller “calibration tag”The “calibration tag” is almost ready functionalities TALK ControllerAll the functionalities will be implemented in the TALK Controller At the moment: Latency1Latency1 (Talk to Tell1)  Mimmo’s Talk ScriptMimmoScript (thanks to Mimmo)

L0TP 2012 runs TALK L0TPIn the 2012 runs the TALK board will be used as L0TP 4 ethernet firmware4 ethernet links allow maximum 4 trigger sources (in this version of the firmware) LEMOsPossibility to have trigger signals from LEMOs TTCTrigger distribution through standard TTC LTU connector choke/error connectorsThe LTU connector and the choke/error connectors were tested

L0TP input buffers4 input buffers TimestampTimestamp addressing inside the memory DelayedDelayed extraction FPGAPipeline processing inside the FPGA  T 0  T 0 =100 ns  T 0 determines the maximum rate (  T 0 =100 ns is possible)  T E jitter latency  T E depends on the jitter in the latency (see Mimmo’s talk) Eth. Input buffer SRAM Delayed extraction (DT) & processing Timestamp addressing time TETE T0T0 Write on the memories Matching of extracted primitives

Status & ToDo Mechanical test Smoke test Electrical test Electrical test plugged on the TELL1 Load Firmware test I2C test Memory test TELL1 communication test Ethernet test TAXI test TTC->TAXI test Translators test LVDS input test L0TP firmware LKr PCs integration test … ECN3 test