CMPUT Computer Organization and Architecture I1 CMPUT229 - Fall 2003 Topic3: Instructions, The Language of the Machine José Nelson Amaral

CMPUT Computer Organization and Architecture I2 Reading Assignment zChapter 3 of Hennessy and Patterson: ySections 3.1 to 3.5.

CMPUT Computer Organization and Architecture I3 Basics of the MIPS Architecture The MIPS architecture has 32 integer registers numbered from 0 to 31. The register 0 always contain the value 0. By software convention these 32 integer registers are divided into subgroup and most of them are referred by a letter and a number. For instance, compilers usually use registers named $s0, $s1, … to contain variables in a C program. Registers named $t0, $t1, … are typically used to store temporary values generated during the computation, but that have no correspondents in the variables in the C program.

CMPUT Computer Organization and Architecture I4 Compiling a C Assignment Using Registers C assignment: f = (g + h) - (i + j) Assumption: f  $s0 g  $s1 h  $s2 i  $s3 j  $s4 MIPS assembly: add $t0, $s1, $s2# $t0  g + h add $t1, $s3, $s4# $t1  i + j sub $s0, $t0, $t1# f  $t0 - $t1

CMPUT Computer Organization and Architecture I5 When Operands are in Memory C assignment: A[12] = h + A[8] Assumption: h  $s2 base of array A  $s3 MIPS assembly: lw $t0, 32($s3)# $t0  A[8] add $t0, $s2, $t0# $t0  h + A[8] sw $t0, 48($s3)# A[12]  $t0

CMPUT Computer Organization and Architecture I6 Memory Organization In MIPS an integer is represented by 4 bytes. A memory address references a single byte. Therefore the difference between the addresses of two consecutive integers in memory is 4. For instance, if the numbers and were stored consecutively in memory at address 0x , the memory would contain: (remember that = ) 0x x x x x x x x x00 0x13 0xFF 0x97 AddressValue In this example, the memory address of is 0x , and the memory address of is 4 bytes ahead at 0x

CMPUT Computer Organization and Architecture I7 Endianess 0x x x x x x x x x00 0x13 0xFF 0x97 AddressValue In the previous example, there are two ways to store at the address 0x and at the address 0x : 0x x x x x x x x x13 0x00 0x97 0xFF AddressValue What is the difference?

CMPUT Computer Organization and Architecture I8 Little-End and Big-End = = 0x Little end of Big end of (binary) (hexadecimal) = = 0xFFFF FF97 Little end of Big end of (binary) (hexadecimal)

CMPUT Computer Organization and Architecture I9 Endianess 0x x x x x x x x x00 0x13 0xFF 0x97 AddressValue The question is: which end of the integer do we store first in memory? 0x x x x x x x x x13 0x00 0x97 0xFF AddressValue Big end of Little end of Little Endian Byte OrderBig Endian Byte Order DECstations and Intel 80x86 are little-endians. Sun SPARC and Macintosh are big-endians.

CMPUT Computer Organization and Architecture I10 Addressing Memory MIPS assembly: lw $t0, 32($s3)# $t0  A[8] add $t0, $s2, $t0# $t0  h + A[8] sw $t0, 48($s3)# A[12]  $t0 Now we can understand the lw and sw instructions in the MIPS Assembly: lw stands for “load word”, and sw stands for “store word”. A word is the most used data unit in a processor. In the MIPS a word has 4 bytes, or 32 bits. lw loads a word from an specified memory location into a register in the processor. sw stores a word from a register in the processor into the specified memory location.

CMPUT Computer Organization and Architecture I11 Addressing Memory MIPS assembly: lw $t0, 32($s3)# $t0  A[8] add $t0, $s2, $t0# $t0  h + A[8] sw $t0, 48($s3)# A[12]  $t0 Destination register for lw Source register for sw Source memory location for lw Destination memory location for sw

CMPUT Computer Organization and Architecture I12 Displacement Addressing Mode MIPS assembly: lw $t0, 32($s3)# $t0  A[8] add $t0, $s2, $t0# $t0  h + A[8] sw $t0, 48($s3)# A[12]  $t0 32($s3) tells the processor to read the value stored in register $s3, add 32 (8 words) to it, and use the result as the memory address for the load instruction

CMPUT Computer Organization and Architecture I13 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0  A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s Address Bus

CMPUT Computer Organization and Architecture I14 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0  A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus

CMPUT Computer Organization and Architecture I15 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0  A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus Data Bus

CMPUT Computer Organization and Architecture I16 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12]  $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s Address Bus Data Bus

CMPUT Computer Organization and Architecture I17 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12]  $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus Data Bus

CMPUT Computer Organization and Architecture I18 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12]  $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus Data Bus

CMPUT Computer Organization and Architecture I19 Representing Instructions: R-Type Instructions add $t0, $s1, $s2# (R8 = $t0, R17 = $s1, R18 = $s2) oprsrtrdshamtfunct R-Type Instruction Format op: Opcode to specify the type of instruction; rs:first register source operand rt: second register source operand rd:register destination operand shamt: used for shift instructions (we will examine them later) funct: function code, specify the variant of the instruction to be executed

CMPUT Computer Organization and Architecture I20 Representing Instructions: R-Type Instructions add $t0, $s1, $s2# (R8 = $t0, R17 = $s1, R18 = $s2) oprsrtrdshamtfunct R-Type Instruction Format In memory we would see: 0x op: Opcode to specify the type of instruction; rs:first register source operand rt: second register source operand rd:register destination operand shamt: used for shift instructions (we will examine them later) funct: function code, specify the variant of the instruction to be executed

CMPUT Computer Organization and Architecture I21 Representing Instructions: R-Type Instructions add $t0, $s1, $s2# (R8 = $t0, R17 = $s1, R18 = $s2) oprsrtrdshamtfunct R-Type Instruction Format In memory we would see: 0x op: Opcode to specify the type of instruction; rs:first register source operand rt: second register source operand rd:register destination operand shamt: used for shift instructions (we will examine them later) funct: function code, specify the variant of the instruction to be executed

CMPUT Computer Organization and Architecture I22 Representing Instructions: R-Type Instructions add $t0, $s1, $s2# (R8 = $t0, R17 = $s1, R18 = $s2) oprsrtrdshamtfunct R-Type Instruction Format In memory we would see: 0x op: Opcode to specify the type of instruction; rs:first register source operand rt: second register source operand rd:register destination operand shamt: used for shift instructions (we will examine them later) funct: function code, specify the variant of the instruction to be executed

CMPUT Computer Organization and Architecture I23 Representing Instructions: I format Instructions lw $t0, 32($s3)# (R8 = $t0, R19 = $s3) # $t0  Memory[$s3 + 32] OpCodersrtaddress I-Type Instruction Format In memory we would see: 0x

CMPUT Computer Organization and Architecture I24 Representing Instructions: I format Instructions lw $t0, 32($s3)# (R8 = $t0, R19 = $s3) # $t0  Memory[$s3 + 32] OpCodersrtaddress I-Type Instruction Format In memory we would see: 0x8E680020

CMPUT Computer Organization and Architecture I25 Representing Instructions: Memory Instructions sw $t0, 1200($t1) # (R8 = $t0, R9 = $t1) # Memory[$t ]  $t OpCodersrtaddress I-Type Instruction Format In memory we would see: 0xAE2404B8

CMPUT Computer Organization and Architecture I26 Representing Instructions: Memory Instructions sw $t0, 1200($t1) # (R8 = $t0, R9 = $t1) # Memory[$t ]  $t OpCodersrtaddress I-Type Instruction Format In memory we would see: 0xAE2404B8

CMPUT Computer Organization and Architecture I27 Instructions for Making Decisions C code: if (i == j) f = g + h; else f = g - h;... Assumption: f  $s0 g  $s1 h  $s2 i  $s3 j  $s4 MIPS assembly: bne$s3, $s4, Else# if i  j goto Else add $s0, $s1, $s2# f  g + h jExit# goto Exit Else:sub$s0, $s1, $s2# f  g - h Exit:...

CMPUT Computer Organization and Architecture I28 Representing Instructions: Branch Instructions bne $s3, $s4, 8  PC  PC + 4 if($1  $2) PC  PC OpCodersrtaddress I-Type Instruction Format MIPS assembly: 0x bne$s3, $s4, Else# if i  j goto Else 0x add $s0, $s1, $s2# f  g + h 0x jExit# goto Exit 0x C Else:sub$s0, $s1, $s2# f  g - h 0x Exit:... In memory we would see: 0x R19 = $s3, R20=$s4 Internally the processor multiplies this constant by 4 to obtain the distance of 8 bytes required.

CMPUT Computer Organization and Architecture I29 Representing Instructions: Jump Instructions j Exit  PC  concat(PC[31-28],IR[25-0])<< OpCodeaddress I-Type Instruction Format MIPS assembly: 0x bne$s3, $s4, Else# if I j goto Else 0x add $s0, $s1, $s2# f  g + h 0x jExit# goto Exit 0x B Else:sub$s0, $s1, $s2# f  g - h 0x Exit:... In memory we would see: 0x

CMPUT Computer Organization and Architecture I30 Representing Instructions: Jump Instructions j Exit  PC  concat(PC[31-28],IR[25-0])<< OpCodeaddress MIPS assembly: 0x bne$s3, $s4, Else# if I j goto Else 0x add $s0, $s1, $s2# f  g + h 0x jExit# goto Exit 0x B Else:sub$s0, $s1, $s2# f  g - h 0x Exit:... PC  PC  0x

CMPUT Computer Organization and Architecture I31 While Loops C code: while (save[i] == k) i = i + j;... Assumption: i  $s3 j  $s4 k  $s5 base of save[ ]  $s6 MIPS assembly: Loop:add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[i]  k goto Exit add$s3, $s3, $s4# i  i + j jLoop# goto Loop Exit: How can we improve this code?

CMPUT Computer Organization and Architecture I32 While Loops C code: while (save[i] == k) i = i + j;... MIPS assembly: Loop:add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit add$s3, $s3, $s4# i  i + j jLoop# goto Loop Exit: load save[i]

CMPUT Computer Organization and Architecture I33 While Loops C code: while (save[i] == k) i = i + j;... MIPS assembly: Loop:add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit add$s3, $s3, $s4# i  i + j jLoop# goto Loop Exit: load save[i] save[i]  k? Exit yes

CMPUT Computer Organization and Architecture I34 While Loops C code: while (save[i] == k) i = i + j;... MIPS assembly: Loop:add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit add$s3, $s3, $s4# i  i + j jLoop# goto Loop Exit: load save[i] i  i + j no save[i]  k? Exit yes

CMPUT Computer Organization and Architecture I35 While Loops C code: while (save[i] == k) i = i + j;... MIPS assembly: Loop:add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit add$s3, $s3, $s4# i  i + j jLoop# goto Loop Exit: load save[i] goto Loop i  i + j no save[i]  k? Exit yes

CMPUT Computer Organization and Architecture I36 While Loops C code: while (save[i] == k) i = i + j;... load save[i] i  i + j goto Loop no save[i]  k? Exit yes i  i + j no load save[i] save[i]  k? Exit yes load save[i] save[i] = k? yes Exit no Before Improvement After Improvement

CMPUT Computer Organization and Architecture I37 While Loops load save[i] MIPS assembly: add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit Loop:add$s3, $s3, $s4# i  i + j add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] beq$t0, $s5, Loop# if save[I]  k goto Exit Exit:

CMPUT Computer Organization and Architecture I38 While Loops load save[i] save[i]  k? Exit yes MIPS assembly: add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit Loop:add$s3, $s3, $s4# i  i + j add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] beq$t0, $s5, Loop# if save[i]  k goto Exit Exit:

CMPUT Computer Organization and Architecture I39 While Loops i  i + j no load save[i] save[i]  k? Exit yes MIPS assembly: add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit Loop:add$s3, $s3, $s4# i  i + j add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] beq$t0, $s5, Loop# if save[i]  k goto Exit Exit:

CMPUT Computer Organization and Architecture I40 While Loops i  i + j no load save[i] save[i]  k? Exit yes load save[i] MIPS assembly: add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit Loop:add$s3, $s3, $s4# i  i + j add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] beq$t0, $s5, Loop# if save[i]  k goto Exit Exit:

CMPUT Computer Organization and Architecture I41 While Loops i  i + j no load save[i] save[i]  k? Exit yes load save[i] save[i] = k? yes Exit no MIPS assembly: add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit Loop:add$s3, $s3, $s4# i  i + j add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] beq$t0, $s5, Loop# if save[i]  k goto Exit Exit:

CMPUT Computer Organization and Architecture I42 While Loops i  i + j no load save[i] save[i]  k? Exit yes load save[i] save[i] = k? yes Exit no MIPS assembly: add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] bne$t0, $s5, Exit# if save[I]  k goto Exit Loop:add$s3, $s3, $s4# i  i + j add$t1, $s3, $s3# $t1  2 * i add $t1, $t1, $t1# $t1  4 * i add$t1, $t1, $s6# $t1  Addr(save[i]) lw$t0, 0($t1)# $t0  MEM[save[i]] beq$t0, $s5, Loop# if save[i]  k goto Exit Exit:

CMPUT Computer Organization and Architecture I43 Set on Less Than Instruction C code: if (a < b) goto Less... Assumption: a  $s0 b  $s1 MIPS assembly: slt $t0, $s0, $s1 # if ($s0 < $s1) $t0  1 else $t0  0 bne $t0, $zero, Less # if $t0  0 goto Less... Less:

CMPUT Computer Organization and Architecture I44 Case/Switch Statement We will use a jump address table to encode the values of the cases and the addresses of the sequence of instructions that should be executed in each case. MIPS has a jump register (jr) instruction to support jump address tables: jr $t1 is an unconditional jump to the address in register $t1

CMPUT Computer Organization and Architecture I45 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i  $s3f  $s0 j  $s4g  $s1 k  $s5h  $s2 4  $t2 Initial address of Jump Table  $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k  4, goto Exit add$t1, $s5, $s5# $t1  2*k add$t1, $t1, $t1# $t1  4*k add$t1, $t1, $t4# $t1  Addr[JumpTable[k]] lw$t0, 0($t1)# $t0  JumpTable[k] jr$t0# jump to address in $t0

CMPUT Computer Organization and Architecture I46 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i  $s3f  $s0 j  $s4g  $s1 k  $s5h  $s2 4  $t2 Initial address of Jump Table  $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k  4, goto Exit add$t1, $s5, $s5# $t1  2*k add$t1, $t1, $t1# $t1  4*k add$t1, $t1, $t4# $t1  Addr[JumpTable[k]] lw$t0, 0($t1)# $t0  JumpTable[k] jr$t0# jump to address in $t0 Step 1: Test if 0  k < 4

CMPUT Computer Organization and Architecture I47 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i  $s3f  $s0 j  $s4g  $s1 k  $s5h  $s2 4  $t2 Initial address of Jump Table  $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k  4, goto Exit add$t1, $s5, $s5# $t1  2*k add$t1, $t1, $t1# $t1  4*k add$t1, $t1, $t4# $t1  Addr[JumpTable[k]] lw$t0, 0($t1)# $t0  JumpTable[k] jr$t0# jump to address in $t0 Step 2: multiply k by 4 to index 32 bit addresses: $t1  4*k

CMPUT Computer Organization and Architecture I48 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i  $s3f  $s0 j  $s4g  $s1 k  $s5h  $s2 4  $t2 Initial address of Jump Table  $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k  4, goto Exit add$t1, $s5, $s5# $t1  2*k add$t1, $t1, $t1# $t1  4*k add$t1, $t1, $t4# $t1  Addr[JumpTable[k]] lw$t0, 0($t1)# $t0  JumpTable[k] jr$t0# jump to address in $t0 Step 3: Load address of Jump Table into $t1

CMPUT Computer Organization and Architecture I49 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i  $s3f  $s0 j  $s4g  $s1 k  $s5h  $s2 4  $t2 Initial address of Jump Table  $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k  4, goto Exit add$t1, $s5, $s5# $t1  2*k add$t1, $t1, $t1# $t1  4*k add$t1, $t1, $t4# $t1  Addr[JumpTable[k]] lw$t0, 0($t1)# $t0  JumpTable[k] jr$t0# jump to address in $t0 Step 4: Load address of code for case in $t0

CMPUT Computer Organization and Architecture I50 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i  $s3f  $s0 j  $s4g  $s1 k  $s5h  $s2 4  $t2 Initial address of Jump Table  $t4 MIPS assembly (cont.): L0:add$s0, $s3, $s4# f  i + j jExit L1:add$s0, $s1, $s2# f  g + h jExit L2:sub$s0, $s1, $s2# f  g - h jExit L3:sub$s0, $s3, $s4# i  i - j Exit:...

CMPUT Computer Organization and Architecture I51 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i  $s3f  $s0 j  $s4g  $s1 k  $s5h  $s2 4  $t2 Initial address of Jump Table  $t4 MIPS assembly (cont.): L0:add$s0, $s3, $s4# f  i + j jExit L1:add$s0, $s1, $s2# f  g + h jExit L2:sub$s0, $s1, $s2# f  g - h jExit L3:sub$s0, $s3, $s4# i  i - j Exit:...

CMPUT Computer Organization and Architecture I52 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i  $s3f  $s0 j  $s4g  $s1 k  $s5h  $s2 4  $t2 Initial address of Jump Table  $t4 MIPS assembly (cont.): L0:add$s0, $s3, $s4# f  i + j jExit L1:add$s0, $s1, $s2# f  g + h jExit L2:sub$s0, $s1, $s2# f  g - h jExit L3:sub$s0, $s3, $s4# i  i - j Exit:...

CMPUT Computer Organization and Architecture I53 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i  $s3f  $s0 j  $s4g  $s1 k  $s5h  $s2 4  $t2 Initial address of Jump Table  $t4 MIPS assembly (cont.): L0:add$s0, $s3, $s4# f  i + j jExit L1:add$s0, $s1, $s2# f  g + h jExit L2:sub$s0, $s1, $s2# f  g - h jExit L3:sub$s0, $s3, $s4# i  i - j Exit:...