1 Memory Management Adapted From Modern Operating Systems, Andrew S. Tanenbaum

2 Memory Management Ideally programmers want memory that is –large –fast –non volatile Memory hierarchy –small amount of fast, expensive memory – cache –some medium-speed, medium price main memory –gigabytes of slow, cheap disk storage Memory manager handles the memory hierarchy

3 Basic Memory Management Monoprogramming without Swapping or Paging Three simple ways of organizing memory (in an operating system with one user process)

4 Multiprogramming with Fixed Partitions Fixed memory partitions –separate input queues for each partition –single input queue

5 Relocation and Protection Cannot be sure where program will be loaded in memory –address locations of variables, code routines cannot be absolute (see next slide) –must keep a program out of other processes’ partitions Use base and limit values –address locations added to base value to map to physical addr –address locations larger than limit value is an error

Seeing the problem extern int x;// placement determined by loader void Fcn (void){int y; x=x+1;} Compiles to: but where is x at runtime? 6 Compiled address (in 32-bit words) instruction [0]define storage for x – outside program 0[function initialization (10 words)] 10load address of x 11load x 12add 1 to x 13store result

7 Swapping (1) Memory allocation changes as –processes come into memory –leave memory Shaded regions are unused memory

8 Swapping (2) a.Allocating space for growing data segment b.Allocating space for growing stack & data segment

9 Page Replacement Algorithms (1) Page fault forces choice –which page must be removed (the “victim”) Modified page must first be saved –unmodified just overwritten Better not to choose an often used page –will probably need to be brought back in soon

10 Page Replacement Algorithms (2) Optimal Page Replacement –Replace page needed at the farthest point in future –Optimal but unrealizable (Why?) FIFO Not Recently Used (NRU) Clock Second Chance Least Recently Used (LRU) rarely implemented - why? Not Frequently Used (NFU) Aging Working Set WSClock

11 Design Issues for Paging Systems Local versus Global Allocation Policies Original configuration Local page replacement Global page replacement

12 Virtual Memory Paging (1) The position and function of the MMU

13 Paging (2) The relation between virtual addresses and physical memory addres- ses given by page table

14 Page Tables (1) Internal operation of MMU with 16 4 KB pages = = = bits for real address 16-bit vaddr Remaining 8 pages not mapped

15 Page Tables (2) 32 bit address with 2 page table fields 8 bytes/entry OK for 32-bit machine 64-bit machine needs 2 52 entries >30GB Top-level page table Second-level page tables

16 Page Tables (3) Typical page table entry

17 TLBs – Translation Lookaside Buffers A TLB to speed up paging

18 3 table schemes Inverted table 1 entry/page in memory PID+V. Page# See cs

Problem with IPT’s Virtual-real translation harder Cannot use virtpg# as index –must search entire table –On EVERY reference 19

20 Cleaning Policy Need for a background process, paging daemon –periodically inspects state of memory When too few page frames are free –selects pages to evict using a replacement algorithm

21 Load Control Despite good designs, system may still thrash when –some processes need more memory –but no processes need less Solution : Reduce number of processes competing for memory –swap one or more to disk, divide up pages they held –reconsider degree of multiprogramming

22 Page Size Small page size Advantages –less internal fragmentation –better fit for various data structures, code sections Disadvantages –program needs more pages  has larger page table

23 Separate Instruction and Data Spaces One address space Separate I and D spaces

24 Shared Pages Two processes sharing same program sharing its page table

25 References Chapters 8 and 9 :OS Concepts, Silberschatz, Galvin, Gagne Chapter 4: Modern Operating Systems, Andrew S. Tanenbaum X86 architecture – Memory segment – Memory model – IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture –