VMM2 - An ASIC for the New Small Wheels Gianluigi De Geronimo, Alessio D'Andragora, Jack Fried, Neena Nambiar, Emerson Vernon, and Venetios Polychronakos Brookhaven National Laboratory TWEPP 2014 – Aix en Provence, France, September 2014

ASIC for ATLAS Muon Spectrometer Upgrade New Small Wheels sTGC Small Strip Thin Gap Chamber MM MicroMegas (MICROMEsh GAseous Structure) Front-end Electronics (ASIC) more than 2.3 million channels total operate in both polarities of charge sensing element capacitance pF charge meas. up to 2 < 1 fC rms time meas. ~ 100 < 1 ns rms trigger primitives, neighbor meas. low power (< 10mW/ch.), programmable

VMM ASICs VMM1 (2012) 50 mm² 500k MOSFETs (8k/ch.) mixed-signal 2-phase readout 64-ch. ASICs being developed for sTGC and MM VMM2 (2014) 115 mm² > 5M MOSFETs (>80k/ch.) planned deep re-design of VMM1 higher functionality and complexity continuous fully-digital readout VMM3 ( ) 130 mm² > 6M MOSFETs includes L1 handling and SEU-tolerant logic L1H

CA shaper logic neighbor VMM2 Architecture – Front-End, Discrimination trim test adjustable discrimination threshold per channel trimming range: 15 mV in 1m increments comparator hysteresis: ~ 20 mV sub-hysteresis mode: effective discrimination ~ 2 mV neighbor logic: sub-threshold neighbor channels inter-chip communication: for neighbor chips input transistor: PMOS 180 nm x 20 mm, 2 mA input capacitance: optimized for 200 pF, can operate from sub-pF to nF polarity: adjustable positive or negative gain: adjustable 0.5, 1, 3, 4.5, 6, 9, 12, 16 mV/fC (max charge 2 to 0.06 pC) peaking time: adjustable 25, 50, 100, 200 ns leakage-adaptive, DDF shaper, BGR-stabilized baseline, test capacitor, mask power dissipation: ~5.0 mW (~2.4 mW 1.2V

TGC out (ToT, TtP, PtT, PtP) CA shaper logic neighbor time peak VMM2 Architecture – Peak/Time and Direct Outputs trim test peak detection: measurement of peak amplitude and storage in analog memory sub-mV resolution on amplitude measurements time detection: measurement of peak timing and storage in analog memory sub-ns resolution, low time-walk on peak time measurement adjustable time-to-amplitude converter (TAC): 125, 250, 500, 1000 ns multi-phase offset-cancellation circuits optional current output for current-mode ADCs power dissipation: ~ V direct digital output: LVDS 600 mV +/- 150 mV selectable meas.: - time-over-threshold (ToT) - threshold-to-peak (TtP) - peak-to-threshold (PtP) - pulse at peak (PtP) continuous self-reset operation

+_+_ C hold R hold peak timing affected by voltage-dependent input offset provides low resolution output for current-mode ADC Current output peak detector i out_low-resol. 6-7 bit rail-to-rail differential input (required from low-voltage CMOS)

+_+_ R hold i out_low-resol. 6-7 bit i out_high-resolution bit input offset is cancelled provides both low- and high- resolution outputs for ADCs Multi-Phase Current-Output Peak Detector

CA shaper logic neighbor 6-b ADC time peak VMM2 Architecture - 6-bit ADC TGC clock trim TGC out (ToT, TtP, PtT, PtP, 6bADC) test lower-resolution ADC: - 6-bit, 1.8-mW, adjustable conversion time and offset - clock-less single-phase current-mode domino architecture - at threshold-crossing, completes in 25 ns from peaktime at direct output: flag at peak followed by serialized address clock frequency: up to 200 MHz selectable serialized mode: either at each clock cycle or at each clock edge continuous self-reset operation

25ns 50ns 75ns 100ns 125ns 150ns 175ns 200ns CK charge event analog pulse OUT peak-found end of conversion end of encoding reset end (ready for next event) timing edgeD5 - D0 conversion completes within ~25 ns from pulse peak dead time from charge event < 100 ns 6-bit amplitude D5-D0 shifted at each ck cycle or at each ck edge Direct Output with 6-bit ADC

Gray count CA shaper logic neighbor addr. 6-b ADC 12-b BC 10-b ADC 8-b ADC BC clock time peak 4X FIFO TGC clock trim TGC out (ToT, TtP, PtT, PtP, 6bADC) test 12-bit timestamp: 12-b Gray-code counter on BC provides timing TAC stop complete timing info: 20-b, ~100 µs, sub-ns res. 4-deep FIFO VMM2 Architecture - 10-b/8-b ADCs, Tstamp, FIFO higher-resolution ADCs: - 10-bit, 200 ns, 1.5 mW, for peak amplitude - 8-bit, 100 ns, 1.5 mW for peak timing (relative to BC) - adjustable conversion time and offset - clock-less current-mode domino architecture - dual-phase: 6+4 bit and 5+3 bit respectively continuous self-reset operation

CA shaper logic neighbor addr. 6-b ADC flg1-bit thr1-bit addr6-bit ampl10-bit time8-bit BC12-bit 12-b BC Gray count 10-b ADC 8-b ADC BC clock logic analog1 (peak) time peak VMM2 Architecture - Multiplexing and Readout 4X FIFO data1 data/TGC clock mux tk clock trim TGC out (ToT, TtP, PtT, PtP, 6bADC) reset test sparse readout of amplitude/timing with token passing readout options: mixed-signal 2-phase: peak and time at analog outputs analog1,2 (peak,time) address serialized at digital output data1 fully digital continuous: 38-bit event data at digital outputs data1,2 data1 also serves as empty flag data shift at each ck cycle or at each ck edge designed for up to 200 MHz data clock 64 channels data2 analog2 (time) 38-bit

or ART (flag + serial address) ART clock VMM2 Architecture - Address in Real Time (ART) address of first event (ART): - available at dedicated LVDS output - first event flag followed by serialized event address - shifted at each ck cycle or at each ck edge - up to 200 MHz clock, self-reset CA shaper logic neighbor addr. 6-b ADC 12-b BC Gray count 10-b ADC 8-b ADC BC clock logic analog1 time peak 4X FIFO data1 data/TGC clock mux tk clock trim TGC out (ToT, TtP, PtT, PtP, 6bADC) reset test 64 channels data2 analog2

coarse time counter: 12-bit Gray-code test pulse generator: 10-bit adjustable coarse threshold generator: 10-bit adjustable temperature sensor: ~ 725 mV mV/°C configuration registers: 80-bit + 24-bit / channel PROMPT (courtesy of CERN): export regulations (ITAR) compliance circuit analog1 data1 data2 analog2 CA shaper logic or neighbor addr. 6-b ADC flg1-bit thr1-bit addr6-bit ampl10-bit time8-bit BC12-bit ART (flag + serial address) ART clock 12-b BC Gray count 10-b ADC 8-b ADC BC clock logic time peak VMM2 Architecture - ASIC 4X FIFO data/TGC clock mux tk clock pulser trim bias registers tp clock TGC out (ToT, TtP, PtT, PtP, 6bADC) tempDAC reset test 64 channels analog mon. technology: IBM CMOS 130nm size: 13.5 mm x 8.4 mm power dissipation: 7-10 mV/ch W/cm² transistor count/ch.: > 80,000 prompt

64 inputs, 9 preamplifier supply (1.2V) analog, mixed-signal, digital supplies (1.2V) – neigh.b – TGC outs analog, mixed-signal, digital supplies (1.2V) – neigh.t – digital IOs (14) - TGC outs 0-6 TGC outs 7-42 Layout and Packaging 13.5 mm 392 bonding pads custom 400-pin 21 x 21 mm² BGA

Current Status VMM2 dies received from foundry in May 2014 Packaged samples received on Sept. 18 th (considerable delay in packaging process) and are being assembled on AZ PCB Dies wire-bonded on Sept. 15 th made possible preliminary tests

Preliminary Results (4-days on wire-bonded die) Configuration and analog (both polarities) appear to work fine Relevant issues so far: Readout modes (2-phase and fully digital) appear to work fine simultaneous high-resolution and direct-output not included in this design, will be added to VMM2a or VMM3 direct timing outputs disabled - mistake in interconnects ADCs accumulations in MSBs - may be e due to power distribution peak detectors too fast decay ~ 2.5mV/µs in voltage mode - from new config. noise added in current mode ? readout: threshold-bit not consistent - found issue in logic locking ? - depending on relative clocks

Flag, threshold, address, amplitude, timing, timestamp appear correct Preliminary Results Digital readout in single and dual data / clock ch 52 D0 D1 ckdt cktk ckbc D0 D1 ckdt cktk ckbc

Neighbor logic, and chip-to-chip communication appear correct Issue with threshold bit in lower channels Preliminary Tests Digital readout with neighbors ch 0 ch 1 trigger to neighbor chip

Up to four events are buffered: channel FIFO appears to work fine Preliminary Results Digital readout with FIFO for 6-event burst ch 52

Amplitude and timing: accumulations in MSBs, noise higher than expected Stronger accumulations observed in other channels. No missing bits. Preliminary Results Interface with Amplitude (top) and Timing (bottom) ADCs ch 63

ART flag and address properly serialized Preliminary Results ART output in single and dual data / clock ch 50 ART ckart ART ckart

Preliminary Results ART response to 5-event burst ch 50 ART auto-reset at end of serialization works fine

taskstatus VMM2 design / fabrication complete Jan Feb 2014 / March - May 2014 BGA package complete expected May 2014 – received Sep 18 th 2014 PCB (AZ)complete VMM2 tests in progress preliminary tests on die started Sep 15 th 2014 VMM SEU & L1H circuitsin progress VMM2a or VMM3 design queued start Jan 2015 Schedule Nachman Lupu (Technion Haifa, Israel) - Lorne Levinson (Weizmann Inst., Israel) Ken Johns, Bill Hart, Dan Tompkins (Univ. Arizona, USA) - George Iakovidis (NTU Athens, Grece) Sorin Martoiu (IFIN-HH Bucharest, Romania) - Jay Chapman (Michigan Univ., USA) Alessandro Marchioro (CERN) - Jessica Metcalfe (BNL, USA) - John Oliver (Harvard, USA) Veljko Radeka (BNL, USA), CERN, ATLAS Collaboration Acknowledgment

Conclusions VMM2 is a planned deep redesign of VMM1 to bring us closer to final VMM Complex design (80k MOSFETs/ch.) with associated risks resolution may be affected by mixed-signal cross-talk locking conditions may occur from complex control logic performance (INL, DNL,..) of novel ADCs to be verified Very preliminary tests on wire-bonded die (4-days) Most of the functionality appear to work fine Relevant issues: direct outputs disabled, ADCs linearity and noise may be below expected, possible locking condition Extensive measurements will be done on just-received packaged samples VMM2a or VMM3 design will be queued pending further results