Beam Secondary Shower Acquisition System: RF Front-End Design (3) Student Meeting Jose Luis Sirvent PhD. Student 2/09/2013

Resolver X Axis: Optical position sensor Y Axis: Diamond Detector Our goals and reasons for pCVD New prototype of BWS ongoing System without bellows All mobile parts in vacuum Position sensing by Optical Encoder Particle shower sensing by pCVD – Need of new readout electronics with high dyn.range – Initial calculations show that our needs are 1e6 – Development of a simpler system (less adjustments as possible) – Current system  Scintillator +PMT + Filters Control of PMT Gain & Filter used Need to know the beam characteristics to set-up the system PMT Saturation effect leads to un precise measurements For more information about the new BWS: X Axis  Optical position sensor measurements Y Axis  Diamond Detector measurements

Some work already carried out Studies carried out for the moment (With 4 reports available): – pCVD Signal estimations from Wire Scanners Initial estimations to delimitate the max and min values of Charge from the pCVD to measure – Impact of Long Cables (250m of CK50) in the pCVD Signal (Report) First approach in the CK50 cable modelling through Pspice, study of Bandwidth and dispersion – BWS Scan Simulation Though Long CK50 Cables (Report) Simulation of a whole wire scan through filters ‘Similar’ to the cable response – QIE10 Research and Review (Report) Study of the QIE10 as possibility for the charge acquisition of the detector – CK50 Cable Measurements in the SPS for BWS Prototype location (Report) Development of a reliable cable model CK50 studies of the impact on the signal for different lenghs, attenuation, bunch overlap..etc. Comparison with real measurements of 175m of CK50 in BA5 SPS location.

Decisions to take for the design pCVD Detector Amplification & Splitting Filters ADC Conversion pCVD Detector Amplification & Splitting ADC Conversion FPGA Platform FPGA Platform Optical Link FPGA Platform Optical Link pCVD Detector Signal Splitting QIE10 Conversion FPGA Platform pCVD Detector Signal Splitting QIE10 Conversion FPGA Platform Optical Link FPGA Platform Optical Link TunnelSurface A) B) C) D)

Tools for decision Development of a Matlab Simulation GUI – Beam profile from Beam parameters – Selection of cable model and length – BWS parameters configurations – Gains / Attenuations in lines – Inclusion of noise in the lines – Filters for signal shaping – ADC Scheme digitalization – QIE10 Scheme digitalization Analysis done for both digitalization schemes: – Influence of cable length for single bunch sigma – Influence of noise in lines for single bunch sigma – Influence of shaping techniques to improve SNR – Influence of # Points per sigma QIE10 Quantification error influences in our measurements Errors in sigma determination <1%

Tools for decision Example of digitalization with noise (Sigma=6.4mV) ADC Shaper Off QIE10ADC Shaper On

Tools for decision Example of cable length impact and compensation with shaper

1. Tunnel Acquisition based on CMS HCAL We had a small meeting with Tullio Grassi 21/08/2013: – – Development of QIE10 Cards for HF Front-End still ongoing, no clear date for availability – They have a small issue due the GBT (Serializer for VTTX), more tests needed Looking for possible alternatives – This board cannot work alone, needed ngCCM board to provide clock and communication. – They have a big arquitecture with many modules and a protocol to manage them – Tullio Suggestion: “You can try to build your own simplified version of our board customized for your pourposes, maybe other experiments also interested in such development” “We are considering the use of the new FPGA IGLOO2 with serializer but studies are ongoing to verify its radiation tolerance” CMS TECHNICAL DESIGN REPORT FOR THE PHASE 1 UPGRADE OF THE HADRON CALORIMETER.CERN-LHCC , CMS-TDR September 2012

Without GBTx but with GOL maybe it’s enough for us – In CMS they needed GBTx for two reasons: A) Clock delivery and phase adjustment: GBTx can deliver 8 clocks and modify independently the phase B) The number of channels they use per card is 12, information of 6 QIE’s for each GBTx in 25ns as far as I know… C) They need bi-directional communication at high speeds – If we are able to deliver the LHC clock from the surface and tune it’s phase… (From BOBR Board) A) We’d already have the clock for the whole FE Readout module, FPGA, GOL and QIE10 B) With GOL we are able to transmit up to 1.6Gbps (40bits in 25ns  Effective 32bits = 2x8 ’TDC’ + 2x8 ‘Charge’) C) GOL works only in one direction T  S. For control (S  T) max speed 700Mbps, working directly with FPGA I/O’s? D) A simplified version of their system could be possible at a glance, but needed to go into details and testing for verification. 1. Tunnel Acquisition based on CMS HCAL (1) GOL Fast Ethernet 8B/10B 1.6Gbps Byte/Bit Bits for 8B/10B protocol 1QIE10 A Charge 2QIE10 A TDC 3QIE10 B Charge 4QIE10 B TDC QIE10 Output Data Format GOL Possible data Output Format (25ns)

1. Tunnel Acquisition based on CMS HCAL (1) -20dB pCVD Attenuator Cividec Diamond Detector -6dB DC-4GHz Splitter -6dB -20dB Tunnel Termination 50Ω Coax link (~5m) Fc= 5 Hz Low Pass Filter DC QIE10 (A) QIE10 (B) FPGA ProASIC3L GOL 1.6Gbps VTX VTX Power LHC Clk Fibre Optic 250m Link Control 2 x QIE10 TDC & Charge LHC Clock 40.08Mhz FE-BWS Readout Module HV LV RS232 Or USB For Program / Debug

1. Tunnel Acquisition based on CMS HCAL (2) -20dB pCVD Attenuator Cividec Diamond Detector -6dB DC-4GHz Splitter -6dB -20dB Tunnel Termination 50Ω Coax link (~5m) Fc= 5 Hz Low Pass Filter DC QIE10 (A) QIE10 (B) FPGA Igloo2 VTX Power LHC Clk Control 2 x QIE10 TDC & Charge LHC Clock 40.08Mhz FE-BWS Readout Module HV LV RS232 Or USB For Program / Debug Fibre Optic 250m Link

2. FPGA selection (Not trivial) From Microsemi ( ProASIC3L family – Family ProASIC3 studied under radiation. C. Poivey, M. Grandjean, and F. Guerre, “Radiation Characterization of Microsemi ProASIC3 Flash FPGA Family Actel, “Customer Notice 1010: RT ProASIC3 Single Event Latch-Up” D. Hiemstra and E. Blackmore, “LET spectra of proton energy levels from 50 to 500 MeV and their effectiveness for single event effects characterization of microelectronics”, J. Schwank, M. Shaneyfelt, J. Baggio et al., “Effects of particle energy on proton-induced single-event latchup” G. Allen, S. McClure, S. Rezgui et al., “Total Ionising Dose Characterization Results of Actel Proasic3, Proasic3L, and IGLOO Flash-based Field Programmable Gate Arrays” – Initial selection for CMS HF FE Readout. – No Serializers, needed GOL for 2xQIE10 700Mbps DDR, LVDS-Capable I/Os – Available Eval-Board for ProASIC3E (~500$) – Available Eval-Board for ProASIC3L (~600$) – Available RTProASIC3 (Radiation Tolerant) in Eval-Board Igloo2 family – Completelly new FPGA – Studies under radiation ongoing… – Single Event Upsets (SEU) immune Flash based – 65nm technology – 5Gbs Serializer/Deserializer (No need of GOL or GBT) – SEU tolerant memories – Soon available evaluation Board, temporal offer 99$!

3. How to start with all this… From the beginning: – 1.Building already some physical blocks of the system – 2.Interconnect them together and start programming – 3.Laboratory verification of the system response and “Proof of Concept” – 4.Once verified then start building first FE prototype – 5.Initial verifications of prototype FE… and start with Back-End FPGA Dev. Board A (Surface Board) FPGA Dev. Board B (Tunnel Board) VTTX Board VTTX Board QIE10 Board pCVD Splitter GOLVTX QIE10 A QIE10 B Computer System Testing and Motorization CLK Control Data Fibre-Optic Link SMF

A) Versatile Transciver (VTRx) – RadHard Lasers and Photodiodes (1MGy) – Already included TIA (Transimpedance Amplif.) – Already indcluded LDD Controls the working point of the Lasers Programmable by I2C – Direct Connection with GBT & GOL? Differential lines tx & rx – Posibility to connect to FPGA’s Diff I/O’s? It will work with at speeds < 4.5Gbps? LVPECL, LVDS, B-LVDS, and M-LVDS – Working up to 5GBPS – Specifications according the SFP+ Module MSA – Working options: LD & PD at 850nm for MMF LD & PD at 1310nm for SMF 4. Some details about components

B) Gigabit Optical Link (GOL) – Serializer for Optical links with 8b/10b & CIMT encoding – Radiation Hard ASIC – Works with LHC clock, Internal Pll & Clock generators – Already used successfully by BLM System and ‘old’ CMS HF FE electronics – I2C programable – Laser output & Differential output – Speeds up to 1.6Gbps – 32 paralel bits input – As soon as GBTx is finished and available it will be obsolete. 4. Some details about components CMS HCAL HF FE

5. The seed is growing: Integration in current systems QIE10 (A) QIE10 (B) FPGA Igloo2 VTX Power LHC Clk Control2 x QIE10 TDC & Charge LHC Clock 40.08Mhz FE-BWS Readout Module LV RS232 Or USB For Program / Debug Fibre Optic 250m Link Tunnel ? SFP + BLEPM Mezzacine Board DAB64x VME Board FPGA Cyclone-5 JTAG FPGA Statrix Back plane VME64 Connector LHC Clock From BST System (BOBR board) Approach A (BLM + BWS): VME Crate Beam Synchronization: BOBR board pCVD Acquisition: DAB64x + BLEPM Mezzanine Very few processing in FPGA’s (communication) Quick Integration in current sytems. How to send the clock??

6. Meeting with Anne Dabrowsky CMS BHM/BCM

7. Alternative option (CMS Inspired): GLIB QIE10 (A) QIE10 (B) FPGA Igloo2 VTX Power LHC Clk Control2 x QIE10 TDC & Charge LHC Clock 40.08Mhz FE-BWS Readout Module LV RS232 Or USB For Program / Debug Fibre Optic 250m Link Tunnel ? LHC Clock From BST System (BOBR board) Approach B (BHM + HCAL): uTCA Crate Beam Synchronization: AMC13 Board pCVD Acquisition: GLIB board Some CMS support needed Radical change on the system (New boards, non BLM Standard) GLIB board is good for test-bench system (quick prototyping) How to send the clock?? Through GLIB Further studies needed… *This picture is inverted

8. What is nice from GLIB? Quick prototyping, PC Connection (PCIe), TTC…

9. Further studies are needed… Could this be realizable? Are all components available? Radiation tolerances? (QIE10) Communication protocols BE-FE Timing & Synchronization QIE10’s …