Chip design and mass test system development Y. Kwon (Yonsei Univ.)

First real scale prototype chip from CERN

Our involvement Participation in chip design Preparation of mass test system

Chip design opportunities Interesting approach based on CIS technology Good (fabrication) potential in Korea Experience for next generation Si sensor possibility in Korea Requirement for expertise : Joint efforts with Prof. M. K. Dongguk Univ.

Our task Take part in development team and contribute. –Appreciation by the design team Gain experience – 학습, 새로운 국내 과제 도출

Cartoon for the pixel

Simple pixel simulation initiated (Whole doping profile)

Simple pixel simulation initiated (E-field, biased electrodes) 6V

Charge injection as current source

Resulting voltage

Front end under study

Experiment study of strong interaction & Si sensor Lab. Dept. of Physics, Yonsei Univ.

Experiment study of strong interaction & Si sensor Lab. Dept. of Physics, Yonsei Univ.

Sub-threshold MOS operation Large gain like BJT Low power But, delicate fabrication and noise are among the main issues.

Status Appreciation by the design tem 활용 과제 가능성 탐색

Issue for the mass test system 50k delicate pixel sensors –Test configuration Probe card Chuck Test definition : Laser, readout –Automation (machine vision + robot, commercial solution available) To pick chips from tray, load them on chuck, test them according to the test configuration, and return to the holder. Minimum system to do custom chip test. Or, something physicists have to do.

PAD layout Total 103 pads to make contact

PAD size We want dual pin contact for each pad.

Probe needle layout Invisible Chip

Specification x 2 = 206 pins LEDs to check probe card position by eye. 4. Contact status check at every 10 ms. 5. Contact status report by ethernet. 0. Dual pins for each pad Pin A for external connection (power/ground/IO), Pin B to check pin contact with the pad relays as switches when we decouple pin A and pin B

Algorithm to check contact 1.Disconnect power/input using relay. 2.Send 1.8(V) logic pulse to each digital input pad via pin A and read pin B. If no pair read back, raise chuck via . If any pair reads back, 3. Start careful adjustment  ’. 4. Send 1.8(V) sequential logic pulse to other digital input pad via pin A and read pin B. 5.Raise  ’ up until all input pad pairs read back. 6.Send 1.8(V) sequential logic pulse to digital input pads via pin A and read pin B. (We will skip step 6 if we worry damage by electrical shock).

7. Raise  ’ up until all input pad pairs read back. 8. FPGA pull down for power pin B, FPGA pull up for ground pin B. 9. Disconnect FPGA output for pin A. 10. Connect power. 11. Check FPGA pin status 12. Raise  ’ up until all pin B status is OK. 13. Disconnect pin B for analog input. Use LED to display current status properly. FPGA flexibility enables variation of algorithm.

Pin A Pin B Input

Probe board FPGA CPU 8 Layer board ETHERNET

Programming option Computer + ethernet –Slow, but flexible On-board CPU –In-between FPGA –Fast, but limited

FPGA programing by VHDL

Transparent chuck? Suction control One hole Would sensor be flat on the chuck?

Chucks in preparation We are evaluating the optimal configuration.

Status Optimization in progress with the delivery of proto type sensor. R&D in coordination with CERN --- We exchange experiences.