Lab 2 Basic Gates in a PLD Module M2.3 Section 4.2 Experiment 2 (p. 63)

Slides:

Advertisements

Similar presentations

Modulo-N Counters Module M10.4 Section 7.2.

Advertisements

Shift Registers Module M11.1 Section 7.3.

7-Segment Displays Lecture L6.1 Section 6.3. Turning on an LED.

Binary Counters Module M10.3 Section 7.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.

ECE 2373 Modern Digital System Design Exam 2. ECE 2372 Exam 2 Thursday March 5 You may use two 8 ½” x 11” pages of information, front and back, write.

A Programmable Logic Device Lecture 4.3. A Programmable Logic Device Multiple-input Gates A 2-Input, 1-Output PLD.

Digital Electronics Dan Simon Cleveland State University ESC 120 Revised December 30, 2010.

The GAL16V8 PLD Module M2.1 Chapter 4. Basic PLD Structure.

08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:

SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 – Part 1.

WinCupl Module M2.2 Section 4.2. Experiment 2 CUPL Header.

Equality Detector Module M5.1 Section 6.1. Equality Detector XNOR X Y Z Z = !(X $ Y) X Y Z

Lab 1 Structure of a PLD Module M1.4 Experiment 1 (p. 40)

EET 1131 Unit 4 Programmable Logic Devices  Read Kleitz, Chapter 4.  Homework #4 and Lab #4 due next week.  Quiz next week.

Programmable Array Logic (PAL) Fixed OR array programmable AND array Fixed OR array programmable AND array Easy to program Easy to program Poor flexibility.

Example 1 Identify Functions Identify the domain and range. Then tell whether the relation is a function. Explain. a. b. SOLUTION a. The domain consists.

Circuit, State Diagram, State Table

TOPIC : Introduction to Functional Modeling UNIT 1: Modeling Digital Circuits Module 1 : Functional Modeling.

Microprocessor Address Decoding.

1 EE121 John Wakerly Lecture #4 Combinational-Circuit Synthesis ABEL.

1 Lecture #10 EGR 277 – Digital Logic Multiplexers (Data Selectors) A multiplexer (MUX) is a device that allows several low-speed signals to be sent over.

Basic Digital Logic 2 Combinational Logic

Gates and Logic Dr John Cowell phones off (please)

1 CS 151: Digital Design Chapter 3: Combinational Logic Design 3-1Design Procedure CS 151: Digital Design.

1 Multiplexers (Data Selectors) A multiplexer (MUX) is a device that allows several low-speed signals to be sent over one high-speed output line. “Select.

Circuit Minimization.

S3 INNOVATION ELECTRONICS. LESSON TITLE: ELECTRONICS Learning Intention: To understand when to use different types of logic gates Activity: Building own.

AND Gate Inputs Output Input A (Switch) Input B (Switch) Output Y (Lamp) 0 (Open) 0 (OFF) A B Lamp.

Circuit Synthesis A logic function can be represented in several different forms:  Truth table representation  Boolean equation  Circuit schematic 

Logic Gates Digital Logic Design. What is a logic gate? A switch with an output that will only turn on when inputs are in particular positions.

Lab 07 :Converting an older IC technology drill machine to VHDL: Slide 2 Slide 3 Generate a Truth Table from an Equation Generate a Truth Table from a.

Combinational Design, Part 2: Procedure. 2 Topics Positive vs. negative logic Design procedure.

Grade 7 Chapter 4 Functions and Linear Equations.

Programmable Logic Devices

EET 1131 Unit 4 Programmable Logic Devices

Activity 1 5 minutes Grab a whiteboard and pen, come to the front and work out the Truth Table for the following circuit: R A B C Q.

Dr.Ahmed Bayoumi Dr.Shady Elmashad

Homework Reading Machine Projects Labs

Logic Gates Binary Day 3 PEOPLE 2016.

Eng. Mai Z. Alyazji October, 2016

Logic Gates Practical Objective: to develop an understanding of logic circuits and truth tables.

Figure 1.1 The Altera UP 1 CPLD development board.

CSC205 Jeffrey N. Denenberg Lecture #5

Memory Interfacing.

Lab02 :Logic Gate Fundamentals:

Basic Digital Logic.

CR 245L Digital Design I Lab Sum of Products, 7-Segment Display,

Programmable Logic Devices

Logic Gates Practical Objective: to develop an understanding of logic circuits and truth tables.

More about DesignWorks

C Graphing Functions.

Digital Fundamentals Tenth Edition Floyd Chapter 11.

Design Example “Date of Birth Problem”

y x y = x + 2 y = x + 4 y = x – 1 y = -x – 3 y = 2x y = ½x y = 3x + 1

Logic Gates Truth Table Challenge

Programmable Logic Devices

Programmable Logic Devices

Objective- To use an equation to graph the

PROGRAMMABLE LOGIC DEVICES (PLD) UNIT-IV

y x y = x + 2 y = x + 4 y = x – 1 y = 6x – 3 y = 2x y = ½x y = 3x + 1

FIGURE 5-1 MOS Transistor, Symbols, and Switch Models

Eng. Ahmed M Bader El-Din October, 2018

Introduction to Logic diagrams and truth tables

Introduction to Logic diagrams and truth tables

Logic Gates and Memory.

SYEN 3330 Digital Systems Chapter 2 – Part 1 SYEN 3330 Digital Systems.

Presentation transcript:

Lab 2 Basic Gates in a PLD Module M2.3 Section 4.2 Experiment 2 (p. 63)

Experiment 2

CUPL Header

CUPL Comments

CUPL Inputs and Outputs

CUPL Logic Equations

CUPL Chip Diagram in.DOC File

Fuse Plot for !X

Structure of the GAL 16V8 PLD

Fuse Plot for !Y

Structure of the GAL 16V8 PLD

Fuse Plot for X & Y

Structure of the GAL 16V8 PLD

Fuse Plot for !(X & Y)

GAL 16V8 Polarity Control OE X A B C X closed B = 0 C = A open B = 1 C = !A Polarity Pin

Fuse Plot for X & Y

Fuse Plot for !(X & Y)

Fuse Plot for X # Y

Structure of the GAL 16V8 PLD

Fuse Plot for !(X # Y)

Fuse Plot for X $ Y

Structure of the GAL 16V8 PLD

Fuse Plot for !(X $ Y)

JEDEC File

JEDEC File Header

JEDEC File Fuse Map

Experiment 2 Basic Gates Modify the file, Exp2.pld, by using pins 6 and 7 for the two inputs X and Y respectively. Modify the simulation file, Exp2.si on the web to use your header. Compile the program using WinCupl and run the simulation. Print out the chip diagram from the.DOC file. Print out the fuse maps. Program the GAL 16V8 chip.

Experiment 2 Basic Gates Connect pins 6 (X) and 7 (Y) to Out1 and Out0. Connect pins to In4-In1. Print the truth table. Label each output column with the appropriate gate. Connect pins to In4-In1. Print the truth table. Label each output column with the appropriate gate. Explain the fuse maps.