io School of Microelectronic Engineering Lecture IV B

School of Microelectronic Engineering Front-end Fabrication steps up to the formation of individual transistors which electrically isolated Back-end Fabrication steps to connect every single transistors until completed Front-End/Back-end Processes

School of Microelectronic Engineering Front-end Process OXIDATION DIFFUSION DEPOSITION LITHOGRAPHY ION IMPLANTATION

School of Microelectronic Engineering OXIDATION PURPOSE: TO GROW SILICON OXIDE FILM WHAT IS OXIDATION? A PROCESS OF ‘GROWING’ SILICON OXIDE ON A WAFER, EITHER ON BARE SILICON OR EXISTING SILICON OXIDE LAYER PROCESS EQUATIONS Si + O 2 SiO 2 (dry oxidation) Si +2H 2 O SiO 2 + 2H 2 (wet oxidation)

School of Microelectronic Engineering O 2 /H 2 O DIFFUSE TO SILICON WAFER/OXIDE LAYER AND REACT WITH Si WHEN REACTION ON SURFACE IS DONE, THICKER FILM WILL REQUIRE THE REACTANT SPECIES TO DIFFUSE DEEPER INTO SILICON (Deal-Groove Linear - Parabolic Model)

School of Microelectronic Engineering GENERALLY AT HIGH TEMPERATURE OF ºC. GASES USED ARE BASICALLY O 2, OR H 2 AND O 2. DILUTED PROCESS WHERE SMALL AMOUNT OF O 2 WITH N 2 AS DILUTER TO GET LOWER GROWTH RATE (FOR BETTER CONTROL OF VERY THIN OXIDE) O 2 ALONE IS CALLED DRY OXIDATION H 2 AND O 2 IS CALLED WET OXIDATION

School of Microelectronic Engineering FURNACE SYSTEM FOR OXIDATION VERTICAL FURNACE

School of Microelectronic Engineering FURNACE SYSTEM FOR OXIDATION HORIZONTAL FURNACE

School of Microelectronic Engineering GAS SOURCE QUARTZ DOOR PADDLE BOAT DUMMY WAFERS

School of Microelectronic Engineering DIFFUSION PURPOSE: TO DRIVE IN DOPANT INTO CERTAIN DEPTH IN SEMICONDUCTOR SUBSTRATE AFTER ION IMPLANTATION PROCESS OR SPIN ON DOPANT TECHNIQUE

School of Microelectronic Engineering DEPOSITION PURPOSE:TO DEPOSIT MATERIALS SUCH AS NITRIDE, OXIDE, POLYSI ETC METHODS PECVD LPCVD SACVD PVD EVAPORATION

School of Microelectronic Engineering * High proportion of the total product use Polysilicon H 2 N 2 SiH 4 * AsH 3 B 2 H 6 PH 3 Exhaust Via Vacuum Pumps and Scrubber 3 Zone Temperature Control Gas Inlet Vertical LPCVD Furnace Quartz Tube Chemical Reactions Nitride Deposition: 3 SiH NH 3  Si 3 N H 2 Polysilicon Deposition: SiH 4  Si + 2 H 2 Process Conditions (Silicon Nitride LPCVD) Flow Rates: sccm Temperature: 600 degrees C. Pressure: 100 mTorr Nitride NH 3 * H 2 SiCl 2 * N 2 SiH 4 * SiCl 4 Poly or nitride p- silicon epi layer p+ silicon substrate

School of Microelectronic Engineering PHOTOLITHOGRAPHY A process for producing highly accurate, microscopic, two dimensional patterns in a photosensitive material. These patterns are replicas of master pattern on a durable photomask, typically made of a thin patterned layer of chromium on a transparent glass plate. The process is repeated many times to build an integrated circuit

School of Microelectronic Engineering

SEM Photolithography Process Flow Nine basic microlithographic process steps PRIME Chill Plate to cool wafer APPLY RESIST SOFT BAKE IMAGING PEB DEVELOP Hard bake Implant or Etch SEM Cluster lithocell

School of Microelectronic Engineering Photoresist Patterning After development Exposure silicon resist Oxide / nitride silicon resist Photomask After etch silicon resist

School of Microelectronic Engineering Photolithography room Photolithography area is yellow- lighted to prevent exposure of photoresist coated wafers to the light. It is a class-10 clean room and is the highest level of cleanliness in the clean room suite.

School of Microelectronic Engineering p- epi p+ substrate field oxide photoresist Photoresists Negative Photoresist * Positive Photoresist * Other Ancillary Materials (Liquids) Edge Bead Removers * Anti-Reflective Coatings * Adhesion Promoters/Primers (HMDS) * Rinsers/Thinners/Corrosion Inhibitors * Contrast Enhancement Materials * Developers TMAH * Specialty Developers * Inert Gases Ar N 2 Photoresist Coating Process

School of Microelectronic Engineering p- epi p+ substrate field oxide photoresist Expose Kr + F 2 (gas) * Inert Gases N 2 Exposure Process

School of Microelectronic Engineering Well Implants Channel Implants (Vt adjust) Source/Drain Implants To introduce impurities into substrate by bombardments of ions Ion Implantation

School of Microelectronic Engineering 180 kV Resolving Aperture Ion Source Equipment Ground Acceleration Tube 90° Analyzing Magnet Terminal Ground 20 kV FocusNeutral beam and beam path gated Beam trap and gate plate Wafer in wafer process chamber X - axis scanner Y - axis scanner Neutral beam trap and beam gate Gases Ar AsH 3 B 11 F 3 * He N 2 PH 3 SiH 4 SiF 4 GeH 4 Solids Ga In Sb Liquids Al(CH 3 ) 3 * High proportion of the total product use junction depth Process Conditions Flow Rate: 5 sccm Pressure: Torr Accelerating Voltage: 5 to 200 keV

School of Microelectronic Engineering Etch Thin Films Photo- lithography Cleaning Front-End Processes Etch Ion Implantation Planarization Test & Assembly Design Wafer Preparation Conductor Etch Poly Etch and Silicon Trench Etch Metal Etch Dielectric Etch

School of Microelectronic Engineering Conductor Etch * High proportion of the total product use Etch Chambers Cluster Tool Configuration Transfer Chamber Loadlock Wafers RIE Chamber Transfer Chamber Gas Inlet Exhaust RF Power Wafer Polysilicon Etches HBr * C 2 F 6 SF 6 * NF 3 * O 2 Aluminum Etches BCl 3 * Cl 2 Diluents Ar He N 2 Chemical Reactions Silicon Etch: Si + 4 HBr  SiBr H 2 Aluminum Etch: Al + 2 Cl 2  AlCl 4 Process Conditions Flow Rates: 100 to 300 sccm Pressure: 10 to 500 mTorr RF Power: 50 to 100 Watts

School of Microelectronic Engineering * High proportion of the total product use Etch Chambers Cluster Tool Configuration Transfer Chamber Loadlock Wafers RIE Chamber Transfer Chamber Gas Inlet Exhaust RF Power Wafer Contact locations Chemical Reactions Oxide Etch: SiO 2 + C 2 F 6  SiF 4 + CO 2 + CF CO Process Conditions Flow Rates: 10 to 300 sccm Pressure: 5 to 10 mTorr RF Power: 100 to 200 Watts Plasma Dielectric Etches CHF 3 * CF 4 C 2 F 6 C 3 F 8 CO * Diluents Ar He N 2 CO 2 O 2 SF 6 SiF 4 Dielectric Etch

School of Microelectronic Engineering Thin Films Photo- lithography Cleaning Front-End Processes Etch Ion Implantation Planarization Test & Assembly Design Wafer Preparation Critical Cleaning Photoresist Strips Pre-Deposition Cleans Cleaning

School of Microelectronic Engineering Contact locations RCA Clean SC1 Clean (H 2 O + NH 4 OH + H 2 O 2 ) * * SC2 Clean (H 2 O + HCl + H 2 O 2 ) * Piranha Strip * H 2 SO 4 + H 2 O 2 * Nitride Strip H 3 PO 4 * Oxide Strip HF + H 2 O * Solvent Cleans NMP Proprietary Amines (liquid) Dry Cleans HF O 2 Plasma Alcohol + O 3 Dry Strip N 2 O O 2 CF 4 + O 2 O 3 Process Conditions Temperature: Piranha Strip is 180 degrees C.

School of Microelectronic Engineering Back-end Process Lithography CVD Dielectrics CVD Tungsten PVD Metal Planarization local (deposit-etch) global (CMP)

School of Microelectronic Engineering Thin Films Photo- lithography Cleaning Front-End Processes Etch Ion Implantation Planarization Test & Assembly Design Wafer Preparation Chemical Vapor Deposition (CVD) Dielectric CVD Tungsten Physical Vapor Deposition (PVD) Chamber Cleaning

School of Microelectronic Engineering * High proportion of the total product use CVD Dielectric O 2 O 3 TEOS * TMP * TEOS Source LPCVD Chamber Transfer Chamber Gas Inlet Exhaust RF Power Wafer Metering Pump Inert Mixing Gas Process Gas Vaporizer Direct Liquid Injection Chemical Reactions Si(OC 2 H 5 ) O 3  SiO CO + 3 CO H 2 O Process Conditions (ILD) Flow Rate: 100 to 300 sccm Pressure: 50 Torr to Atmospheric Dielectric CVD

School of Microelectronic Engineering Tungsten CVD * High proportion of the total product use CVD Dielectric WF 6 * Ar H 2 N 2 Output Cassette Input Cassette Wafer Hander Wafers Water-cooled Showerheads Multistation Sequential Deposition Chamber Resistively Heated Pedestal Chemical Reactions WF H 2  W + 6 HF Process Conditions Flow Rate: 100 to 300 sccm Pressure: 100 mTorr Temperature: 400 degrees C.

School of Microelectronic Engineering PVD Barrier Metals SiH 4 Ar N 2 Ti PVD Targets * Physical Vapor Deposition Chambers Cluster Tool Configuration Transfer Chamber Loadlock Wafers PVD Chamber Transfer Chamber Cryo Pump Wafer NSN + e - Backside He Cooling Argon & Nitrogen Reactive Gases DC Power Supply (+) * High proportion of the total product use Process Conditions Pressure: < 5 mTorr Temperature: 200 degrees C. RF Power:

School of Microelectronic Engineering * High proportion of the total product use Chamber Cleaning C 2 F 6 * NF 3 ClF 3 Water-cooled Showerheads Multistation Sequential Deposition Chamber Resistively Heated Pedestal Chemical Reactions Oxide Etch: SiO 2 + C 2 F 6  SiF 4 + CO 2 + CF CO Process Conditions Flow Rates: 10 to 300 sccm Pressure: 10 to 100 mTorr RF Power: 100 to 200 Watts Aluminum Surface Coating Process Material Residue Chamber Wall Cross-Section Chamber Cleaning

School of Microelectronic Engineering Planarization Thin Films Photo- lithography Cleaning Front-End Processes Etch Ion Implantation Planarization Test & Assembly Design Wafer Preparation Oxide Planarization Metal Planarization

School of Microelectronic Engineering Planarization (Chemical Mechanical Polishing) * High proportion of the total product use. Platen Polishing Head Pad Conditioner Carousel Head Sweep Slide Load/Unload Station Wafer Handling Robot & I/O Polishing Pad Slurry Delivery Platen Wafer Carrier Wafer Backing (Carrier) Film Polyurethane Pad Polyurethane Pad Conditioner Abrasive CMP (Oxide) Silica Slurry KOH * NH 4 OH H 2 O CMP (Metal) Alumina * FeNO 3 Process Conditions (Oxide) Flow: 250 to 1000 ml/min Particle Size: 100 to 250 nm Concentration: 10 to 15%, 10.5 to 11.3 pH Process Conditions (Metal) Flow: 50 to 100 ml/min Particle Size: 180 to 280 nm Concentration: 3 to 7%, pH *