12004 MAPLD Int’l Conference – Paper 118 Kumar Automated FSM Error Correction for Single Event Upsets Dr. Nand Kumar & Darren Zacher Design Creation and Synthesis Division Mentor Graphics Corp.

22004 MAPLD Int’l Conference – Paper 118 Kumar Introduction/Agenda n Challenges n Proposal n Methodology n Results n Discussion n Lessons Learned n Conclusions

32004 MAPLD Int’l Conference – Paper 118 Kumar Challenges n Harsh operating environments – Single Event Upsets (SEUs) are to be expected – Significant design, verification and operational challenges n Increasing pressures to control costs – Accelerated design, verification and deployment cycles – Use of lower-cost parts and smaller device geometries to accommodate increasing gate count n Dilemma!

42004 MAPLD Int’l Conference – Paper 118 Kumar Proposal (1/4) n Add Hamming error checking bits based on state encoding – O(log 2 n) extra storage for parity bits – Parity logic corrects single-bit errors – Can add extra parity bit to detect double-bit errors

52004 MAPLD Int’l Conference – Paper 118 Kumar Proposal (2/4) n Hamming distance increased to three

62004 MAPLD Int’l Conference – Paper 118 Kumar Proposal (3/5)

72004 MAPLD Int’l Conference – Paper 118 Kumar Proposal (4/5)

82004 MAPLD Int’l Conference – Paper 118 Kumar Proposal (5/5) n Proposed benefits – Fewer extra storage elements required than TMR – Correction in combinatorial logic, less susceptible to errors, especially in antifuse devices – Can detect double-bit errors with low overhead – Not limited by the FSM encoding

92004 MAPLD Int’l Conference – Paper 118 Kumar Methodology n Consider several state machines – Various state encodings – Various state counts n Compare and contrast error correction – Hamming encoding of state bits – Triple Module Redundancy n Target Actel 54SX72A-STD – Constrain minimally for synthesis and layout – Prevent register replication n Simulate using bit error injection – Forced state / hamming parity bits to 0 or 1 n Models “persistent SEU”

MAPLD Int’l Conference – Paper 118 Kumar Results (1/7) n Circuit characteristics – Original encodings (TMR)

MAPLD Int’l Conference – Paper 118 Kumar Results (2/7) n Circuit characteristics – Original encodings (Hamming)

MAPLD Int’l Conference – Paper 118 Kumar Results (3/7) n Circuit characteristics – Original encodings

MAPLD Int’l Conference – Paper 118 Kumar Results (4/7) n Circuit characteristics – Minimal encodings (TMR)

MAPLD Int’l Conference – Paper 118 Kumar Results (5/7) n Circuit characteristics – Minimal encodings (Hamming)

MAPLD Int’l Conference – Paper 118 Kumar Results (6/7) n Circuit characteristics – Minimal encodings

MAPLD Int’l Conference – Paper 118 Kumar Results (7/7) n Bit error susceptibility – Simulated FSM2 RTL vs. synthesized gates with 1,000 random stimulus patterns n One state bit forced – No errors – Upset(s) corrected n One parity bit forced – No errors – Upset(s) corrected n Two bits forced – Errors found – Initial results encouraging

MAPLD Int’l Conference – Paper 118 Kumar Discussion n Hamming encoding more area efficient than TMR for minimal encodings n Metastability issues?

MAPLD Int’l Conference – Paper 118 Kumar Lessons Learned n Hamming correction overhead comes at a performance price n Performance penalty larger for one-hot state encoding n Hamming error recovery will not incur frequency penalty

MAPLD Int’l Conference – Paper 118 Kumar Conclusions n Hamming encoding an acceptable alternative to TMR n Hamming encoding lends itself well to automated implementation during synthesis n Error susceptibility advantages – Double-bit errors detectable with Hamming n Scales well with FSM state count n Area penalty half that of TMR for minimal encoding