Objectives : At the end of this lesson, students should be able to : i.Identify the types of memory chip and their functions. ii.Define the difference between full and partial address decoder. iii.Design address decoder using full and partial technique Chapter 9 Memory in 68K System

9.1 Types Of Memory Chapter 9 Memory in 68K System a) ROM (Read Only Memory) Containing permanent or semi-permanent data Non-volatile; even after turn off supply, the contents of ROM will remain Used to store a program Types available in market a)ROM (Read-Only Memory) - program by manufacture, can’t reprogram b) PROM (Programmable ROM) - can be program once only using PROM programmer c) EPROM (Erasable PROM) - can be program using PROM programmer, has quartz window to delete program using UV d) EEPROM (Electrically EPROM) - can be program using PROM programmer, can overwrite previous program

9.1 Types Of Memory Chapter 9 Memory in 68K System Data bus OE CS V PP Address bus A 0 – A n D 0 – D n EPROM + 5V GND CS* OE*Description Chip deactivate, use minimum power 0 0Read cycle : data are put in bus 0 1Standby cycle : data are put faster when OE* arrive PinDescription A 0 – A n Connected to lower connection in uP address bus D 0 – D n Connected to data bus CS* (Chip Select)Make the chip function OE* (Output Enable) Cause ROM to put data in bas data V pp (Programming Voltage) Use by EPROM programmer to change the bit value in chip

9.1 Types Of Memory Chapter 9 Memory in 68K System b) RAM (Random Access Memory) Containing none permanent data Volatile, so data stored in RAM stays there only as long the supply is turn on Used to store a temporary data Types available in market a) SRAM (Static RAM) - easy to fabricate (4 transistor to store one bit), fast, suitable for system with small memory b) DRAM (Dynamic RAM) - easy to fabricate (1 transistor to store 1 bit), compact storage, used for main memory of PC c) EDORAM (Extended Data Output RAM) d) BEDORAM (Burst EDORAM) e) SDRAM (Synchronous DRAM) f) DDR-DRAM (Double Data Rate-Synchronous DRAM)

9.1 Types Of Memory Chapter 9 Memory in 68K System Data bus OE CS WE Address bus A0 – A n D0 – D n SRAM + 5V GND CS* OE* WE*Description 1 X XChip deactivate, use minimum power 0 0 0Can’t be describe. Refer data sheet 0 0 1Read cycle : data are put in the bus 0 1 0Write cycle : data in the bus is latch 0 1 1Standby cycle : Fast operation when OE arrive PinDescription A 0 – A n Connected to lower connection in uP address bus D 0 – D n Connected to bas data CS* (Chip Select)Make the chip function OE* (Output Enable) Cause RAM to put data in bas data WE* (Write Enable)Cause data in bus to be store

9.2 Address Decoder Chapter 9 Memory in 68K System Why we need address decoder ? The is connected to many devices via its bus system. However only one device can communicate with the in one time. Address decoder is used to select device to be activated. Function: to monitor the state of address bus and determine when the device should be activated. Address bus Chip Selection Decoder Address Top part of address bus Bottom part of address bus

9.2 Address Decoder Chapter 9 Memory in 68K System How address decoder function ? Address bus Decoder Address EPROM or SRAM Valid address Initially, decoder will wait specified pola exist in address bus. This condition happen when AS = 0. When the condition exist, SEL will be given (0) to active. SEL will activate pin CS and cause selected memory devices to be choose.

9.2 Address Decoder Chapter 9 Memory in 68K System Types of decoder Full address decoder - All address line must be used to access each physical memory location, either to access data or activate selected device Partial address decoder - Not all the address line available for address decoding - Simple and least expensive - Decoder chip can be used: a) 3 to 8 decoder (74LS138) b) 2 to 4 decoder (74LS139)

9.3 Designing Full Address Decoder Chapter 9 Memory in 68K System Steps : a) Determine address range for each component - Based address (Start address) - Size - End address b) Determine address lines that will be link to memory and to decoder - Find total address line directly connected from uP to memory - Lower address line connected to memory - Balance of address line connected to decoder

9.3 Designing Full Address Decoder Chapter 9 Memory in 68K System Example : A system containing 64k word (128k byte) of RAM will be interface with 68K. Based address $ Design the address decoder. Steps : a) Determine address range for each component Based address : $ Size: 128KB End address: Based Address + (Size in Hex) - 1 : $ $20000 – 1 : $49FFFF

9.3 Designing Full Address Decoder Chapter 9 Memory in 68K System b) Determine address lines that will be link to memory and decoder. $ = % – start address $49FFFF = % – end address - Start from the right - Bit that start with 0 at start address and end with 1 at end address directly go to memory - For this example A1 – A16 will directly connected to memory. A0 signal will be brought out through UDS/LDS pins. - A17 to A23 will be connected to address decoder Memory (A1-A16) UDS*/LDS* Decoder (A17-A23)

9.3 Designing Full Address Decoder Chapter 9 Memory in 68K System c) Design the circuit to detect AS=0 and A23-A17 to A23 A22 A21 A20 A19 A18 A17 SEL* AS* Note: NAND gate only have 2, 3, 4 and 8 inputs.

9.4 Designing Partial Address Decoder Chapter 9 Memory in 68K System Steps : a) For every chip, determine address range for each component - Based address - Size - End address b) For every chip, determine the total address lines directly go to memory - Find total address lines at chip - Lower address lines from uP directly go to memory c) Based on the balance address lines and total devices, use decoder to activate one device at a time.

9.4 Designing Partial Address Decoder Chapter 9 Memory in 68K System Example : Design a partial address decoder in order to make uP able to communicate to each of device below. i) ROM chips starts at $ contain a total of 16k word (32k byte) ii) RAM chips starts at $ contain a total of 64k word (128k byte) iii) I/O chip allocate at address $ until $80001F (32 address) Steps : a) For every chip, determine address range for each component ROM i) Based address : $ Size: 32KB End address= Based Address + (Size in Hex) - 1 = $ $8000 – 1 = $007FFF

9.4 Designing Partial Address Decoder Chapter 9 Memory in 68K System RAM Based address : $ Size: 128KB End address= Based Address + (Size in Hex) - 1 = $ $20000 – 1 = $41FFFF I/O Based address : $ End address: $80001F

9.4 Designing Partial Address Decoder Chapter 9 Memory in 68K System Steps : Mark the address line that the has ‘0’ at based address and ‘1’ at end address with ‘X’ in table b) For every chip, determine the total address lines directly go to memory ROM : address line A1 to A14 RAM : address line A1 to A16 I/O: address line A1 to A4 c) Choose minimum address line to select one of the 3 devices. A23 and A22

9.4 Designing Partial Address Decoder Chapter 9 Memory in 68K System Not used Memory Map $00 7FFF $41 FFFF $80 001F Not used $ $3F FFFF $ $7F FFFF $ $ $ $ $FF FFFF

9.4 Designing Partial Address Decoder Chapter 9 Memory in 68K System Memory Map Not used

9.5 Logic Control For R/W Memory Chapter 9 Memory in 68K System UPRD LORD UPWR LOWR UDS LDS R/W

9.4 Designing Partial Address Decoder Chapter 9 Memory in 68K System Tutorial 1.A total of 16K word of EPROM section, with a starting address of $300000, is to be added to an existing memory system. Design a full address decoder and draw the memory map. 2.Two chips of 8K word EPROM with starting address of $ and two chips of 8K word RAM with starting address of $700000, are needed for a new memory system. Design a full address decoder for the system and draw the memory map. Then, design the memory system using partial address decoder (use 74LS139).

9.4 Designing Partial Address Decoder Chapter 9 Memory in 68K System Tutorial 3.The following figure shows a full address decoder for a 68k memory system. The memory system consists of EPROM and RAM. From the figure, obtain the total size of each EPROM and RAM, then the start and end address.

Rujukan i.Antonakos, J. L., The Microprocessor: Hardware and Software Principles and Applications 5th edition, Prentice Hall, ii. Clements, A., Microprocessor Systems Design: Hardware, Software, and Interfacing 3rd edition, PWS, iii. Tocci, R. J., Digital Systems: Principles and Applications 9th edition, Prentice Hall,2004. iv.Floyd, T. L., Digital Fundamentals 8th edition, Prentice Hall, v.Spasov, P., Microcontroller Technology: The 68HC11 and 68HC12 5th edition, Prentice Hall, Chapter 9 Memory in 68K System