Phase-II strips update S. Díez, 22 Mar 2013

S. Díez, Phase-II strips update Outline  Recent activities at Berkeley (What’s new since January)  US stavelet: a double-sided stave(let) prototype  Bus tape co-curing activities  Summary of Phase-II strips meeting at Berlin this week  Layout notes: latest simulation results  250 nm program: mechanical/electrical update  130 nm program: schedule, costs, activities  Sorry, not possible to include global support and integration progress: too much information here already! 22 Mar 20132

S. Díez, Phase-II strips update A reminder: 250 nm strip modules 22 Mar 2013 Short strips sensor Short strips hybrid BCCs and data lines Power line Individual module test frame ASICs connected to strips via wire bonds (128 per ASIC) 97.5 mm 3

S. Díez, Phase-II strips update A reminder: stave core 22 Mar 2013  Staves require support structures (cores) with low mass, embedded cooling pipes, good thermal performances, resistance to deformations, flat structure  Carbon composites: very flexible class of materials, reasonable Xo, good thermal properties, variable CTE  Carbon fiber “sheets” consist of filaments or woven layers impregnated with epoxy.  By arranging layers in various lay-ups and configurations, a great variety of components can be created with enhanced mechanical and thermal properties. Ti coolant tube Carbon honeycomb Carbon fiber facing (3 lay-ups) Readout ICs Si Strip sensor Kapton flex hybrid Cu bus tape (co-cured with facings) Stave cross-section High T conductivity foam 4

S. Díez, Phase-II strips update Motivation and features of US stavelet  Shield-less tape: Al shielding layer removed from tape; CF acts as effective shielding  Reduces the material budget of the tapes by ~ 50% (8-10% reduction overall stave)  Co-curing complexity greatly reduced (deformations become marginal)  Tape costs reduced  Shield left at one module position for comparison  First double-sided stavelet prototype, one side DC-DC, other side serial 22 Mar 2013 Baseline layoutShield-less tape 5

S. Díez, Phase-II strips update Stavelet core  Tapes co-cured in between CF layups  Last CF layer acts as shielding  Co-cured on flat surface Mostly flat, except small deformations near the Al region  Plastic + Al lateral inserts to accommodate power circuitry 22 Mar \90\tape\0 6

S. Díez, Phase-II strips update US stavelet so far  Both sides fully loaded  Modules from Berkeley and Santa Cruz 22 Mar 2013 LBL-07SC-03SC-02SC-01 LBL-06LBL-03LBL-02LBL-01 DC-DC SP, chain of modules See 2013 annual meeting talk for more details on core construction, metrology, and module assembly 7

S. Díez, Phase-II strips update DC-DC vs. SP side (I): ENC noise at 1 fC 22 Mar DC-DC side SP CoM side 8

S. Díez, Phase-II strips update DC-DC vs. SP side (II): DTNoise & summary 22 Mar 2013 Thres. Module 3Module 2Module 1, Al shieldedModule 0 C0C1C2C3C0C1C2C3C0C1C2C3C0C1C2C3 1 fC fC fC Thres.Module 3Module 2Module 1, Al shieldedModule 0 C0C1C2C3C0C1C2C3C0C1C2C3C0C1C2C3 1 fC fC fC DC-DC side SP CoM side  Results consistent both with DC-DC and UKSP2 stavelets at RAL (CERN)  Minimal differences among Al shielded and shieldless modules on the stavelet  ENC slightly lower for SP stavelet (~ 20e difference)  Analogous DTN results 9

S. Díez, Phase-II strips update Low inductance referencing strips 22 Mar 2013  Low inductance GND reference in between hybrids of the same module required  Shieldless tape, cannot use shield as low inductance reference in between hybrids  Misaligned Cu squares on shieldless tape, cannot use them either  Referencing strips:  BCC and power side references completely independent of each other Power side BCC side 10

S. Díez, Phase-II strips update CM removal capacitive links  DTNoise heavily affected by CM noise developed along the data lines  CM removal capacitors (100 nF) between Data shield and BCC GNDs:  What happens if they are NOT there (SP side): 22 Mar 2013 Thres.Module 3Module 2Module 1, Al shieldedModule 0 C0C1C2C3C0C1C2C3C0C1C2C3C0C1C2C3 1 fC fC fC

S. Díez, Phase-II strips update PPB2 and SPP ASIC on SP side  Chain of Modules Power Protection Boards (PPB2), compatible with Serial Power Protection ASIC boards (SPP)  Test bench for SPP ASIC  Work in progress! 22 Mar

S. Díez, Phase-II strips update Bus tape co-curing activities at Berkeley 22 Mar  Tapes layout is performed either at Berkeley or Oxford  Next full length DC-DC stave prototype tapes were designed at Oxford (conservative shielded design), and fabricated at Altaflex Inc. (Santa Clara, CA)  Co-curing of tapes with facings and extensive verification measurements (pre- and post- co-curing) have been recently performed at LBNL

S. Díez, Phase-II strips update Tapes co-curing (I)  Co-curing with three layers of CF ( orientation), 45 gsm  Tapes are cured on the inside of an Al pipe to compensate for bending of the 90 layer and the Al layer  Cable side down + shims to keep CF flat  250 F max T 22 Mar

S. Díez, Phase-II strips update Flatness result 22 Mar

S. Díez, Phase-II strips update Tape measurements 22 Mar

S. Díez, Phase-II strips update Tape measurements pre co-curing  Measurement of all nominal 98 mm separations of HV contact circles (24 in total) with Smartscope  Tapes came typically short by 1 mm from Altaflex, and the shift is flat along the cable 22 Mar

S. Díez, Phase-II strips update Stretch after co-curing 22 Mar

S. Díez, Phase-II strips update What is the source of the effect? 22 Mar

S. Díez, Phase-II strips update Now to Berlin meeting… 22 Mar

S. Díez, Phase-II strips update Layout notes (I) 22 Mar

S. Díez, Phase-II strips update Layout notes (II) 22 Mar Coverage Occupancy Track finding efficiency p T resolution “Stub”

S. Díez, Phase-II strips update Layout notes (III) 22 Mar  LoI Layout is stable  Simulation results are encouraging  Quite satisfied with track finding efficiency and p T resolution  Mis-reconstructed fake rate (fake tracks per real tracks) acceptable  Pixel layout doesn’t affect strips layout as long as it provides 5 hits anywhere  Comments:  Layout group: “Stub layer is essential: better drop the 5th barrel layer than getting rid of the stub”  There is still a strong resistance against it in the strips community Proposed a simulation of 10% failures + dropping the stub layer (worst case)

S. Díez, Phase-II strips update 250 nm program: progress on DC-DC power  DC-DC converters studies: 22 Mar  Tandem DC-DC converters for full length stave 250 Star configuration and separate GND backplane connections Suitable for stave 250  Relocation of DC-DC converter on top of sensor to mimic 130 nm implementation Effects of converter still visible No H pickup, just E (correlated with WB) With appropriate shielding, results are encouraging DCDCDCDC DCDC on ABC130 module

S. Díez, Phase-II strips update 250 nm program: first petal prototypes  A lot of progress since last AUW:  First “petalet” under development Two possible implementations, both DC-DC Lower module built and tested successfully First core fabricated Pocofoam, taped glued on co-cured facings Bus tape layout being worked out 22 Mar

S. Díez, Phase-II strips update 250 nm program: other activities  HV MUX: very encouraging results from first switching circuit prototype (shown at AUW)  Semisouth, provider of rad-hard HV switches (key component of the circuit) went out of business!!  Ongoing market study to find substitute  Construction of stave 250: full length, (double-sided?) prototypes  First one is shielded, DC-DC power, tandem converters  Shieldless serial power stave, new power routing Needs new serial power protection boards Need to find construction/testing sites: Berkeley? CERN?  DAQ software and firmware versions being implemented to read out so many data streams 22 Mar

S. Díez, Phase-II strips update 130 nm program: ABCN130 and HCC  ABCN130 readout ASIC: 130 nm CMOS technology, 256 readout channels/chip  Latest progress by issue found on voltage regulator with simulations: understood  Inclusion of Fast Cluster Finder (self- seeded trigger) quite likely on first version of ABCN130  HCC: 130 nm CMOS  Still under development Delayed submission 22 Mar ABCN130 layout HCC activities/plans:

S. Díez, Phase-II strips update 130 nm program: schedule, chip costs  Submission scenarios:  Next 3 years activities prior to pre- submission in 2018  60 wafers minimum 90% yield, 10% spares:  7000 ABCN (3200B, 2400EC, 1400SM)  920 HCC: (420B, 360EC, 140SM )  3 production runs for ABCNs  CERN fronts the money for first submission 22 Mar ABCN costs

S. Díez, Phase-II strips update 130 nm modules  We actually know how to make decisions (sometimes)! 22 Mar

S. Díez, Phase-II strips update 130 nm program: first tests, first modules  Single ABCN testing PCBs and wafer probing of ABCN130  First 130 nm hybrids will be tested without HCCs  Versatile driver board used for single chip, HCC-less hybrids 22 Mar HCC bypassed – all hybrid connectivity brought to edge and routed to connector With HCC Without HCC Comes on pluggable PCB HCC First tests of HCC come on PCB carrier? Single chip board Wafer probe card Driver board

S. Díez, Phase-II strips update 130 nm program: fast cluster finder demonstrator  Trigger promptly on momenta in 10GeV/c range by looking at correlated offsets in hits on two closely coupled axial layers  640 Mbps data, associate 4 possible combinations, serialize and send cluster segments within 25 ns staying beam synchronous  Proposed demonstrator by Carl  Can be used on beam or comsic ray tests 22 Mar

S. Díez, Phase-II strips update 130 nm program: other activities  EoS board  160 MHz multidrop tests  Understanding SLVDS drivers  Tools for 130 nm modules assembly  Bus tapes  Initial 3 years plan: build 4 stavelets (2DC-DC, 2SP) and petalets  … 22 Mar

S. Díez, Phase-II strips update Local support locking mechanisms  Two options for locking mechanisms  Single-sided mount (UK)  Double-sided mount (US)  Both options seem feasible Integration of DC-DC staves at a 10 o tilt angle very challenging due to converters height 22 Mar

S. Díez, Phase-II strips update Berkeley activities in the near future  Additional US stavelet testing  SP PPB2 boards implementation  Noise injection on data lines  Simultaneous readout of both sides  Bus tapes for 250 nm full length staves and first 130 nm stavelets  Building/testing SP stave 250?  Study effects of different glue patterns on stave mechanical/thermal stability  Study of cable deformation with shieldless tapes  Self seeded trigger demonstrator  130 nm modules and stavelets build site  Development of assembly/test tools  Investigate new EoS interface 22 Mar

S. Díez, Phase-II strips update Backup 22 Mar

S. Díez, Phase-II strips update Mechanical tools for stavelet assembly 22 Mar 2013  Stavelet frame  Core attached with 2 mm dowel pins Holes and slots drilled on core plastic inserts  Vertical 5 mm pins on stavelet frame  Module pickup tool + dowel pins  Based on module construction tools  Linear bearings on pickup tool  Modules picked up from module mounting jig by adding removable dowel pins 36

S. Díez, Phase-II strips update Stavelet assembly procedure 22 Mar 2013  RAL design for glue mask in low tack film  SE4445 T conductive glue, Ag epoxy for HV contact, fishing lines to control glue height  Additional Kapton layer (tape) to avoid short circuit between HV contacts and CF  Module is vacuumed down on the ASICs and picked up from the module construction jig  Linear bearings on the pickup tool fit the vertical pins on the frame  Fishing line controls glue thickness, but it could also be done with washer shims on the pins 37

S. Díez, Phase-II strips update Test setup 22 Mar 2013  Similar setup as for individual modules  Shielding box, NESLAB CFT-33 water chiller running at 6 C, N 2 to avoid moisture  HSIO DAQ and sctdaq software hooked up on EoS  LV power: Sorensen XPF 60-20D; DC-DC: 10.5 V, ~ 11A; SP CoM: 12.3 V, 9.5 A  HV PS: 4-channels VME cards used for SCT modules (Krakow) Custom developed Labview controller Sorensen LV PS 38

S. Díez, Phase-II strips update DC-DC side: thermal performances at 6 o C 22 Mar 2013  Water cooling running at 6 C during stavelet operation  Negative Temperature Coefficient (NTC) thermistors located at the center of each flex hybrid  Relative humidity and Temperature sensors (SHT71) located at the inlet and outlet cooling pipes  DC-DC converters are the main heat sources  T in -T out = 0.8 C  Higher T on Al shielded module Module 3Module 2 Module 1, Al shielded Module 0 T out = 12.7C RH = 7.2% T in = 11.9 C RH = 6.0% 21.1C24.6C25.3C26.1C23.6C23.4C27.5C23.6C 39