Dept. of Electronics Engineering & Institute of Electronics National Chiao Tung University Hsinchu, Taiwan ISPD’16 Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique Wen-Hsiang Chang, Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu, Mango C.-T. Chao National Chiao Tung University Hsinchu, Taiwan Cheng-Hong Tsai, Yen-Chih Chiu Global Unichip Corporation Hsinchu, Taiwan

VLSI Testing NCTU ISPD’16 Outline  Motivation of building a routing-friendly power distribution network (PDN)  Targeted PDN and design environment  Proposed design flow  Experiment results  Conclusion 2

VLSI Testing NCTU ISPD’16 Motivation of a routing-friendly PDN  Meeting IR-drop and EM constraint requires more PDN metal than before due to Smaller voltage supply and higher current density  Such routing resource occupied by PDN may increase the overall routing overhead  Designing a routing-friendly PDN can speed up the design closure at the physical-design stage 3

VLSI Testing NCTU ISPD’16  There is no fast effective routing-cost index when designing a PDN  There are two common routing-cost indexes for a PDN  Total metal area of the PDN  Total wire length of global route associated with the PDN Routing-cost indexes 4

VLSI Testing NCTU ISPD’16 Routing-cost index: total PDN metal area 5 designD1D2D3D4D5D6D7D8avg

VLSI Testing NCTU ISPD’16  An ineffective routing-cost index for a PDN 6 Routing-cost index: total PDN metal area

VLSI Testing NCTU ISPD’16 Routing-cost index: global route result 7 designD1D2D3D4D5D6D7D8avg

VLSI Testing NCTU ISPD’16  Average runtime (minute) of global route  Impractical to run global route for each possible PDN configuration  Our objective is to estimate the total wire length of global route associated with a given PDN by using machine learning techniques 8 Routing-cost index: global route result designD1D2D3D4D5D6D7D8 runtime

VLSI Testing NCTU ISPD’16 Outline  Motivation of building a routing-friendly power distribution network (PDN)  Our targeted PDN and design environment  Proposed design flow  Experiment results  Conclusion 9

VLSI Testing NCTU ISPD’16 M5 M4 M3 M1 power rails M6 power stripes M7 power stripes AP power stripes M2 VDD GND = VDD via array = GND via array = VDD bump pad = GND bump pad  4 layers ： Aluminum-Pad (AP) - M7 - M6 - M1 AP and M7 ： Low-sheet-resistance layer M6, M1 ： High-sheet-resistance layer Targeted PDN 10

VLSI Testing NCTU ISPD’16  Target only the PDN with uniform power stripes for each power layer  That is to say, the stripe width and the pitch between two stripes are the same for a layer  Cadence Encounter as the tool of physical design  PDN in our design flow is built after the placement stage and before the routing stage Targeted PDN and design environment 11

VLSI Testing NCTU ISPD’16 Outline  Motivation of building a routing-friendly power distribution network (PDN)  Targeted PDN and design environment  Proposed design flow  Experiment results  Conclusion 12

VLSI Testing NCTU ISPD’16 Overview of proposed design flow Find the PDN with minimal routing cost while satisfying IR-drop and EM constraints II LIB IR-drop and EM constraint Power pad information Supply voltage Learned routing-cost model Learn the routing-cost model by Gaussian process regression I Training samples of previous designs LEF Targeted block design database 13

VLSI Testing NCTU ISPD’16 Problem formulation of stage I  Objective Represent the total wire length of global route associated with a given PDN as a function of predictor features for the targeted block design  Inputs Training samples of previous block designs 3 training samples of the targeted block design Database of the targeted block design and LEF 14

VLSI Testing NCTU ISPD’16  Output Learned routing-cost model (a function of predictor features)  Advantage Given any untried PDN, the global route result can be fast estimated by the learned routing-cost model instead of time-consuming global route  Limitation Previous block designs and the targeted block design must use the same LEF and PDN structure Problem formulation of stage I 15

VLSI Testing NCTU ISPD’16 Construction of training samples  A training sample consists of One response feature which is the total wire length of global route associated with a PDN Several basic predictor features (the features of the PDN, the design, and the placement)  The procedure of constructing a training sample Construct a PDN configuration (fast) Run global route (slow) Extract the result of global route (fast) Extract basic predictor features (fast) 16

VLSI Testing NCTU ISPD’16 Flow of learning a routing-cost model  Given these training samples, new predictor features are created by Taking square or square root of a basic predictor feature Then by multiplying or dividing two existing predictor features  Value of each predictor feature is normalized to the interval from 0.5 to

VLSI Testing NCTU ISPD’16  Given these response features and predictor features, a routing-cost model is learned by Gaussian Process Regression  In other words, the response feature can be represented as a function of predictor features  Advantage of Gaussian process regression High dimensional model and stable prediction accuracy 18 Flow of learning a routing-cost model

VLSI Testing NCTU ISPD’16 Problem formulation of stage II  Objective Find a PDN configuration with minimal routing-cost while meeting IR-drop and EM constraint  Output ： the PDN configuration Power stripe width on M6, M7, AP layer Number of power stripe on M6, M7 and AP layer 19

VLSI Testing NCTU ISPD’16 Inputs of stage II 20

VLSI Testing NCTU ISPD’16 Evaluation of a PDN configuration  IR-drop & EM evaluation of a PDN configuration Convert the PDN to a conductance matrix (fast) Solve the conductance matrix by a public matrix solver to get the voltage of each node (slow) Calculate IR-drop of each instance (fast) Calculate EM of each segment (fast)  Routing-cost evaluation of a PDN configuration Extract and produce predictor features (fast) Calculate estimated total wire length of global route associated with the PDN by the routing-cost model learned in the previous stage (fast) 21

VLSI Testing NCTU ISPD’16 Irredundant stripe width concept  Advantage of using irredundant stripe widths More routing tracks with the same PDN metal usage Smaller solution space for setting the stripe widths 22 = available track = occupied track (a) redundant stripe width(b) irredundant stripe width = power stripe = interconnect = wasted area W. H. Chang, M. C. T. Chao and S. H. Chen, "Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp , May 2014.

VLSI Testing NCTU ISPD’16 Flow of PDN configuration searching 23

VLSI Testing NCTU ISPD’16 Outline  Motivation of building a routing-friendly power distribution network (PDN)  Target PDN and design environment  Proposed design flow  Experiment results  Conclusion 24

VLSI Testing NCTU ISPD’16 Comparison of learning techniques 25

VLSI Testing NCTU ISPD’16 R squares of learning techniques 26 design instance count R square GPBayesianStepwiseRidgeSVM D1 1073k D2 2835k D3 1759k D4 695k D5 773k D6 74k D7 2239k D8 564k avg

VLSI Testing NCTU ISPD’16 Mean errors of learning techniques 27 design mean error GPBayesianStepwiseRidgeSVM D1 2.29%3.70%3.32%3.83%2.56% D2 1.24%6.04%6.71%5.97%4.29% D3 1.95%4.58%4.29%4.65%4.16% D4 3.40%4.75%5.33%4.90%13.22% D5 2.21%4.50%3.43%4.83%5.31% D6 2.42%4.78%5.05%4.72%8.59% D7 2.32%7.28%7.22%7.31%5.93% D8 2.45%9.06%8.81%9.03%4.58% avg. 2.28%5.58%5.52%5.66%6.08%

VLSI Testing NCTU ISPD’16 Comparison of routing-cost indexes X axis – total metal area of a PDN Y axis – total wire length of detail route associated with a PDN X axis – estimated total wire length of global route associated with a PDN by the learned routing-cost model Y axis – total wire length of detail route associated with a PDN 28

VLSI Testing NCTU ISPD’16  PDN-Metal Search uses the total metal area of a PDN as the routing-cost index Proposed flow vs. PDN-metal search 29 design wire length without PDN (um) proposed flowPDN-Metal Search worst IR-drop (mv) worst EM worst IR-drop (mv) worst EM D114,086,137679, %750, %9.6% D239,135,337372, %398, %6.5% D317,466,048155, %174, %10.7% D410,611,88770, %75, %6.8% D59,198,43032, %45, %27.2% D6611,9246, %10, %37.0% D730,902,62670, %80, %11.7% D815,535,39183, %97, %14.2% avg % %15.5%

VLSI Testing NCTU ISPD’16 Runtime (minute) of different flows  Longest runtime of proposed flow ： 11 hours Affordable for designs (D2, D7) with more than 2-million instance count 30 design comparison D1321m163m12131m D2656m354m35590m D3325m191m10883m D4261m160m8510m D5118m38m5546m D662m21m1391m D7673m464m23217m D8208m107m7607m avg.0.51X37.3X

VLSI Testing NCTU ISPD’16 Conclusion  A machine learning flow is built to find A routing-cost model to estimate global route result  A PDN configuration searching flow is built to find PDN configuration with minimal routing cost while meeting IR-drop and EM constraints  Experiments on 8 industrial block designs show the effectiveness and scalability of the proposed flow 31

VLSI Testing NCTU ISPD’16 Thank you for your listening

VLSI Testing NCTU ISPD’16 Q & A

VLSI Testing NCTU ISPD’16 Irredundant stripe width calculation

VLSI Testing NCTU ISPD’16 Proposed flow vs. [7]  Using an analytical model to build the PDN in [7] may usually lead to over-design for PDN 35 design wire length without PDN (um) proposed flow[7] worst IR-drop (mv) worst EM worst IR-drop (mv) worst EM D114,086,137679, %902, %24.8% D239,135,337372, %1,061, %64.9% D317,466,048155, %465, %66.6% D410,611,88770, %146, %51.9% D59,198,43032, %70, %53.3% D6611,9246, %10, %36.3% D730,902,62670, %239, %70.5% D815,535,39183, %238, %65.0% avg % %54.2%

VLSI Testing NCTU ISPD’16 Basic predictor features  Features of the PDN The total metal usage of power stripes per metal layer The number of power stripes per metal layer The number of routing tracks occupied by a stripe per metal layer The size of a via array and the number of via arrays  Features of the block design and the placement The number of cells and the number of nets The distribution of the number of terminals for a net The total half perimeters of all nets The number of available area for each layer (excluding the existing blockages) 36