CSE477 L25 Memory Peripheral.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 25: Peripheral Memory Circuits Mary Jane Irwin ( ) [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

CSE477 L25 Memory Peripheral.2Irwin&Vijay, PSU, 2003 Review: Read-Write Memories (RAMs)  Static – SRAM l data is stored as long as supply is applied l large cells (6 fets/cell) – so fewer bits/chip l fast – so used where speed is important (e.g., caches) l differential outputs (output BL and !BL) l use sense amps for performance l compatible with CMOS technology  Dynamic – DRAM l periodic refresh required (every 1 to 4 ms) to compensate for the charge loss caused by leakage l small cells (1 to 3 fets/cell) – so more bits/chip l slower – so used for main memories l single ended output (output BL only) l need sense amps for correct operation l not typically compatible with CMOS technology

CSE477 L25 Memory Peripheral.3Irwin&Vijay, PSU, 2003 Review: 2D Memory Bank Row Decoder Read Precharge Precharge Circuit Column Decoder Sense Amps Column Decoder A N-1 … A i A i-1 … A 0 Write Circuitry Sense Amps Write Circuitry data

CSE477 L25 Memory Peripheral.4Irwin&Vijay, PSU, 2003 Peripheral Memory Circuitry  Row and column decoders  Read bit line precharge logic  Sense amplifiers  Read/write circuitry  Timing and control  Speed  Power consumption  Area – pitch matching

CSE477 L25 Memory Peripheral.5Irwin&Vijay, PSU, 2003 Row Decoders  Collection of 2 M complex logic gates organized in a regular, dense fashion  (N)AND decoder for 8 address bits WL(0) = !A 7 & !A 6 & !A 5 & !A 4 & !A 3 & !A 2 & !A 1 & !A 0 … WL(255) = A 7 & A 6 & A 5 & A 4 & A 3 & A 2 & A 1 & A 0  NOR decoder for 8 address bits WL(0) = !(A 7 | A 6 | A 5 | A 4 | A 3 | A 2 | A 1 | A 0 ) … WL(255) = !(!A 7 | !A 6 | !A 5 | !A 4 | !A 3 | !A 2 | !A 1 | !A 0 )  Goals: Pitch matched, fast, low power

CSE477 L25 Memory Peripheral.6Irwin&Vijay, PSU, 2003 Implementing a Wide NOR Function  Single stage 8x256 bit decoder (as in Lecture 22) l One 8 input NOR gate per row x 256 rows = 256 x (8+8) = 4,096 l Pitch match and speed/power issues  Decompose logic into multiple levels !WL(0) = !(!(A 7 | A 6 ) & !(A 5 | A 4 ) & !(A 3 | A 2 ) & !(A 1 | A 0 )) l First level is the predecoder (for each pair of address bits, form A i |A i-1, A i |!A i-1, !A i |A i-1, and !A i |!A i-1 ) l Second level is the word line driver  Predecoders reduce the number of transistors required l Four sets of four 2-bit NOR predecoders = 4 x 4 x (2+2) = 64 l 256 word line drivers, each a four input NAND – 256 x (4+4) = 2,048 -4,096 vs 2,112 = almost a 50% savings  Number of inputs to the gates driving the WLs is halved, so the propagation delay is reduced by a factor of ~4

CSE477 L25 Memory Peripheral.7Irwin&Vijay, PSU, 2003 Split Row Two-Level 8x256 Decoder !(!A 0 & !A 1 & !A 2 )... !(A 0 & A 1 & A 2 ) !(!(!A 0 &!A 1 &!A 2 ) | !(!A 3 &!A 4 &!A 5 ) | !(!A 6 &!A 7 )) *256 WL 255 WL 0 *256 WL 255 WL 0 Address *8 *4  Pitch matched  Buffered word line drivers

CSE477 L25 Memory Peripheral.8Irwin&Vijay, PSU, 2003 Pass Transistor Based Column Decoder BL 3 BL 2 BL 1 BL 0 data_out 2 input NOR decoder A1A1 A0A0 S3S3 S2S2 S1S1 S0S0  Read: connect BLs to the Sense Amps (SA) Writes: drive one of the BLs low to write a 0 into the cell l Fast since there is only one transistor in the signal path. However, there is a large transistor count ( (K+1)2 K + 2 x 2 K ) l For K = 2  3 x 2 2 (decoder) + 2 x 2 2 (PTs) = = 20 !BL 3 !BL 2 !BL 1 !BL 0 !data_out

CSE477 L25 Memory Peripheral.9Irwin&Vijay, PSU, 2003 Tree Based Column Decoder BL 3 BL 2 BL 1 BL 0 A0A0 !A 0 A1A1 !A 1 data_out  Number of transistors reduced to (2 x 2 x (2 K -1)) for K = 2  2 x 2 x (2 2 – 1) = 4 x 3 = 12  Delay increases quadratically with the number of sections (K) (so prohibitive for large decoders) can fix with buffers, progressive sizing, combination of tree and pass transistor approaches !BL 3 !BL 2 !BL 1 !BL 0 !data_out

CSE477 L25 Memory Peripheral.10Irwin&Vijay, PSU, 2003 Decoder Complexity Comparisons  Consider a memory with 10b address and 8b data Conf.Data/RowRow DecoderColumn Decoder 1D8b10b = a 10x2 10 decoder Single stage = 20,480 Two stage = 10,320 2D32b (32x256 core) 8b = 8x2 8 decoder Single stage = 4,096 T Two stage = 2,112 T 2b = 2x2 2 decoder PT = 76 T Tree = 96 T 2D64b (64x128 core) 7b = 7x2 7 decoder Single stage = 1,792 T Two stage = 1,072 T 3b = 3x2 3 decoder PT = 160 T Tree = 224 T 2D128b (128x64 core) 6b = 6x2 6 decoder Single stage = 768 T Two stage = 432 T 4b = 4x2 4 decoder PT = 336 T Tree = 480 T

CSE477 L25 Memory Peripheral.11Irwin&Vijay, PSU, 2003 Bit Line Precharge Logic equalization transistor - speeds up equalization of the two bit lines by allowing the capacitance and pull-up device of the nondischarged bit line to assist in precharging the discharged line !PC !BLBL  First step of a Read cycle is to precharge (PC) the bit lines to V DD l every differential signal in the memory must be equalized to the same voltage level before Read  Turn off PC and enable the WL l the grounded PMOS load limits the bit line swing (speeding up the next precharge cycle)

CSE477 L25 Memory Peripheral.12Irwin&Vijay, PSU, 2003 Sense Amplifiers  Amplification – resolves data with small bit line swings (in some DRAMs required for proper functionality)  Delay reduction – compensates for the limited drive capability of the memory cell to accelerate BL transition SA input output t p = ( C *  V ) / I av large small make  V as small as possible  Power reduction – eliminates a large part of the power dissipation due to charging and discharging bit lines  Signal restoration – for DRAMs, need to drive the bit lines full swing after sensing (read) to do data refresh

CSE477 L25 Memory Peripheral.13Irwin&Vijay, PSU, 2003 Classes of Sense Amplifiers  Differential SA – takes small signal differential inputs (BL and !BL) and amplifies them to a large signal single- ended output l common-mode rejection – rejects noise that is equally injected to both inputs  Only suitable for SRAMs (with BL and !BL)  Types l Current mirroring l Two-stage l Latch based  Single-ended SA – needed for DRAMs

CSE477 L25 Memory Peripheral.14Irwin&Vijay, PSU, 2003 Latch Based Sense Amplifier SE BL isolate  V = 0.1V DD  V = V DD !BL data_out!data_out bit line inputs sense amplifier outputs

CSE477 L25 Memory Peripheral.15Irwin&Vijay, PSU, 2003 Alpha Differential Amplifier/Latch SE data_out  V = V DD !data_out S3S3 S2S2 S1S1 S0S0 column decoder sense amplifier N2 N3 N4 N5 P1P2 P3P4 N1 mux_out sense PC !mux_out 0101 0101 off  on !sense

CSE477 L25 Memory Peripheral.16Irwin&Vijay, PSU, 2003 Read/Write Circuitry D: data (write) bus R: read bus W: write signal CS: column select (column decoder) Local W (write): BL = D, !BL = !D enabled by W & CS Local R (read): R = BL, !R = !BL enabled by !W & CS !BLBL SA D W !R R Precharge Local R/WCS

CSE477 L25 Memory Peripheral.17Irwin&Vijay, PSU, 2003 Approaches to Memory Timing DRAM Timing Multiplexed Addressing RAS CAS RAS-CAS timing Address Bus msb’slsb’s Row Addr. Column Addr. Address Bus SRAM Timing Self-Timed Address Address transition initiates memory operation

CSE477 L25 Memory Peripheral.18Irwin&Vijay, PSU, 2003 Reliability and Yield  Memories operate under low signal-to-noise conditions l word line to bit line coupling can vary substantially over the memory array -folded bit line architecture (routing BL and !BL next to each other ensures a closer match between parasitics and bit line capacitances) l interwire bit line to bit line coupling -transposed (or twisted) bit line architecture (turn the noise into a common-mode signal for the SA) l leakage (in DRAMs) requiring refresh operation  suffer from low yield due to high density and structural defects l increase yield by using error correction (e.g., parity bits) and redundancy  and are susceptible to soft errors due to alpha particles and cosmic rays

CSE477 L25 Memory Peripheral.19Irwin&Vijay, PSU, 2003 Redundancy in the Memory Structure Row address Column address Redundant row Redundant columns Fuse bank

CSE477 L25 Memory Peripheral.20Irwin&Vijay, PSU, 2003 Redundancy and Error Correction

CSE477 L25 Memory Peripheral.21Irwin&Vijay, PSU, 2003 Soft Errors  Nonrecurrent and nonpermanent errors from l alpha particles (from the packaging materials) l neutrons from cosmic rays  As feature size decreases, the charge stored at each node decreases (due to a lower node capacitance and lower V DD ) and thus Q critical (the charge necessary to cause a bit flip) decreases leading to an increase in the soft error rate (SER ) From Semico Research Corp. MTBF (hours).13  m.09  m Ground-based Civilian Avionics System Military Avionics System189 From Actel

CSE477 L25 Memory Peripheral.22Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next lecture l Power consumption in datapaths and memories -Reading assignment – Rabaey, et al, 11.7; 12.5  Reminders l HW#5 due today l Project final reports due on-line by 5:00pm on Friday, December 5 th l Final grading negotiations/correction (except for the final exam) must be concluded by December 10 th l Final exam scheduled -Tuesday, December 16 th from 10:10 to noon in 118 and 113 Thomas