Hervé MATHEZ IPNL CALICE Meeting CERN 12 – PCB with 256 RPCs pads (Status) IPNL - LAL - LLR

Hervé MATHEZ IPNL CALICE Meeting CERN 12 – PCB 256 RPCs pads Status 1.3 PCBs with all components 2.1 PCB without components used to test the pcb Xtalk 3.encountered problems

Hervé MATHEZ IPNL CALICE Meeting CERN 12 – Dig Part64 Pads 1 32 PCB Gnd Generator Scope Shield Xtalk measurements - Setup 64 Pads Small Probe 10µm diameter

Hervé MATHEZ IPNL CALICE Meeting CERN 12 – Xtalk measurements - Setup

Hervé MATHEZ IPNL CALICE Meeting CERN 12 – PCB 8 Layers : 2 face to face paths (2 layers) Hardroc Pin 2-7 (50 Ohms to GND) Pad Input on Rpc Pad = 2V Measure = 3.2 mV Xtalk = 0.16% Input Measure Average of Measure Xtalk measurements

Hervé MATHEZ IPNL CALICE Meeting CERN 12 – layers 8 layers same layer 2 diff layers Coupling Cap 50 fF/cm 120 fF/cm 120fF/cm to 1pF/cm Xtalk 0.3 % 0.4% 0.3% gnd h d w h=50µm,w=200µm,d=330µm C = 50 fF/cm gnd h d w h=200µm,w=200µm,d=330µm C = 120fF/cm gnd h h=100µm,w=200µm w Measurements results depends on shield connection Difficult to conclude what configuration is the best Xtalk < 0.5% Xtalk measurements - Conclusion

Hervé MATHEZ IPNL CALICE Meeting CERN 12 – Board with components

Hervé MATHEZ IPNL CALICE Meeting CERN 12 – Encountered Problems 1 board in test 2 HardRoc in short circuit on Analog Power Supplies :  need to be changed  40 mA/HardRoc Problems with Xilinx power supplies (tps75003) :  Need to add external voltage regulators Foot print problems with USB interface circuit :  Need to do manual connection ! SOLVED Xilinx I/O problems :  Need to add wire and change VHDL code TO BE SOLVED

Hervé MATHEZ IPNL CALICE Meeting CERN 12 – Conclusion 1.2 PCB in Fab (return from Fab next week) 2.After a fully debugging of the first board modified 2 another boards launch 3 last pcb to solder components first tests with 1 RPC connected

Hervé MATHEZ IPNL CALICE Meeting CERN 12 – Conclusion