ASIPP/ EAST Presented by Zuchao Zhang on behalf of EAST Central Control Team 1 Institute of Plasma Physics, Chinese Academy of Sciences Implementation of Central Control System on EAST Superconducting Tokamak 1 Jul 第十六届全国科学计算与信息化会议暨科研大数据论坛 中国. 大连

ASIPP/ EAST CONTENTS Introduction to Central Control System What’s new in CCS - Central Console - Interlock Alarm - Central Safety & Interlock - Discharge Control - Timing & Synchronization Network Central Control Room Summary 2

ASIPP/ EAST 3 CONTENTS Introduction to Central Control System What’s new in CCS - Central Console - Interlock Alarm - Central Safety & Interlock - Discharge Control - Timing & Synchronization Network Central Control Room Summary

ASIPP/ EAST 4 Introduction of EAST Control System

ASIPP/ EAST Introduction of EAST Control System EAST Control and Data Acquisition System 5 Safety & Interlock Network Monitor & Visualization Data Management Data AcquisitionData Analysis Data StorageData Server Plasma Control System Central Control System discharge Control Central Console Central Safety & Interlock Timing & Synchronization Data Network (Ethernet) Timing Network (Optic) RFM Network (Real-Time) Control Network (Ethernet) EASTSubsystems The Scope of EAST Control System

ASIPP/ EAST Central Control System 6 Purpose: To meet the long-pulse requirements Integrate, harmonize and supervise all of subsystem Upgraded CCS has been developed with four goals: a) More friendly man-machine interface (MMI); b) More stable process control and operation supervisory; c) High-precision timing and synchronization; d) More reliable interlock and protection.

ASIPP/ EAST 7 CONTENTS Introduction to Central Control System What’s new in CCS - Central Console - Interlock Alarm - Central Safety & Interlock - Discharge Control - Timing & Synchronization Network Central Control Room Summary

ASIPP/ EAST 8   Central Console Discharge Monitoring (MMI) Subsystem Parameter Setting Discharge Configuration Timing & Synchronization Setting History Recall Signal Test Setting Parameter Archiving Messages Alarm for CCS Free Free Arrive in time Arrive in time Multi-user support Multi-user support Information backup Information backup Offer the operators with kindly interface to control the remote subsystem

ASIPP/ EAST OK 9  Interlock Alarm System ERR Central Safety &Interlock Local Safety &Interlock Interface of Interlock Alarm System Subsystem Status ： Error Alarm ： Safety Protection 18 lines to inspect 15 subsystems 10 I/O lines for 8 subsystems 11 I/O lines to protect the device ~200 events handling last campaign Alarm the operators the status of each subsystems

ASIPP/ EAST 10 SIEMENS S7-400 Stable and Reliable Response delay ~3 ms Redundancy Mechanism Main station: CPU: 417-4H Power supply: PS407 Memory: 2 x 15MB CP Advanced FM350-1 Slave station :ET200M  Central Safety & Interlock Fault Resolution < 1ms Ensure personal and device security Specific error detection algorithm was designed Filter, 3 cycle detection

ASIPP/ EAST 11 Response To Subsystem Subsystem Event  Discharge Control PXI-8110PXI-6259 Event Control the discharge logic

ASIPP/ EAST 12   Timing & Synchronization Discharge Control Database Server Central Console Main Goals  provide timing signals, each subsystem works in the same reference clock  provide triggers signals, control the participation in the experiment of subsystems in time series  perform the processing and recording of externally generated events  acquire the outputs of itself, inspect the operation state Keep the original star-type topology with a central node and several local nodes All the nodes are implemented in the PXI and FPGA industry devices

ASIPP/ EAST Time 75.0n-25.0n Voltage Amplitude Jitter Test Clock ： 10 MHz Sample rate: 12 GS/s Sample ： Periodic jitter ： 218.8p PJ (p-p) ： 668.2p Eye Diagram of Clock after Isolation Devices Sample Histogram of Clock Output Jitter Test Result Accessories Optical Signal Output Electrical Signal Output Isolation Devices Clock Driven Device One to multiple Output

ASIPP/ EAST 参数列表： 每节点通道数 每节点时钟 14 1 st delay time:-5000 ms, pulse width: 500 ms; 2 nd delay time:-4000 ms, pulse width: 500 ms; 3 rd delay time: ms, pulse width: 500 ms; 4 th delay time: ms, pulse width: 500 ms. sig_polarity ： positive CH9 in multi-trigger 8 reference clock signals per node, frequency range: 1Hz ~ 20 MHz. 64 single delay 10 multi-trigger width:1ms-6872s 2 acquisition channels sampling rate: 100 ks/s/ch. 2 event driven Specification

ASIPP/ EAST Core / Convergence / Access Dual Core “ 双核三层 ” 结构 Three Layers Two Core Switches for Redundancy Convergence Layer Core Layer Access Layer Control VLAN Data VLAN Two VLAN Control VLAN / Data VLAN (Giga-bit) 15   Network SmokePing keeps track of network latency Time ： 3 Hours （ 2012/04/05/13:15 ~ 2012/04/05/16:15 ） IP add ： Test results ： RTT (Round-Trip Time) “ 双核三层 ” 结构 Network Latency Measurement a dedicated secure network to support the communication.

ASIPP/ EAST 16 CONTENTS Introduction to Central Control System What’s new in CCS - Central Console - Interlock Alarm - Central Safety & Interlock - Discharge Control - Timing & Synchronization Network Central Control Room Summary

ASIPP/ EAST Central Console More than 20 OPIs Video, Audio, Monitors Remote Control Virtualization 17   Control Room Rich Internet Application (RIA) Virtual Private Network (VPN) XenDesktop virtual desktop

ASIPP/ EAST 18 CONTENTS Introduction to Central Control System What’s new in CCS - Central Console - Interlock Alarm - Central Safety & Interlock - Discharge Control - Timing & Synchronization Network Central Control Room Summary

ASIPP/ EAST Summary More and more new facilities had been used in the system The upgraded central control system have been ready for long pulse to steady state. Future work New timing synchronization system Complex algorithm in the future event handling 19

ASIPP/ EAST Thanks for your attentions ！ 20