Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ Test Results from the VIP1 Chip Grzegorz DEPTUCH Fermi National Accelerator Laboratory, Batavia, IL, USA  focus of this presentation is 1) fabrication process and design of the VIP1 chip 2) test results 3) lesson learnt and preparation of VIP2 on behalf of FERMILAB ASIC Design Group: R. Yarema, G.Deptuch, J.Hoff, A.Shenai, M.Trimpl, T.Zimmerman Computer Division Group: M.Turqueti, R.Rivera and: M.Demarteau, R.Lipton, D.Christian

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ Direction to go:

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ MITLL 3DM2 vertical integration process flow (VIA LAST): Step 1: Fabricate individual tiers Step2: Invert, align, and bond wafer 2 to wafer 1 Step 3: Remove handle silicon from wafer 2, etch 3D Vias, deposit and CMP tungsten oxide bond 3D Via Step 4: Invert, align and bond wafer 3 to wafer 2/1, remove wafer 3 handle wafer, form 3D vias from tier 2 to tier 3, etch bond pads 3 tier chip; 3DM2 includes 2 “digital” 180-nm FDSOI CMOS tiers and 1 RF 180-nm FDSOI CMOS tier 11 metal layers including: 2-μm- thick RF backmetal, Tier-2 backmetal In principle wafer 1 could also be bulk

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ M3 M2 M1 BM1 M3 M2 M1 BM2 CFDRC Full 3D Model with active elements in all layers MIT-LL 3D IC Technology (SOI) - Layer Description from CFDRC 22  m MITLL 3DM2 vertical integration process flow (VIA LAST):

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ Pictures of the VIP1 die: ~700  m Metal fill cut while dicing ~7  m edge view top view

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/  Chip provides both binary and analog hit information  Chip incorporates tiem stamping with 32 time stamps for each ILC train of 2820 BXs (two time stamping schemes implemented for evaluation purposes: analog and digital)  Chip integrates data sparsification (a high speed token passing scheme with look-ahead used to sparsify the hit information)  Chip outputs X and Y location, analog pulse height and time stamp for each hit (tiem stamp and hit pulse stored in each pixel, X/Y addresses generated at the perimeter)  Chip transmits all digital information off the chip on one serial output line withing the train interval  The analog pulse height and time stamp are read out on separate lines  Chip may read only hit pixels or all channels (readALL mode)  The power dissipation/cell is within the ILC requirements (with pulsed powering)  Pixel size is 20×20  m 2  Design is adequate for a 1k×1k array but is lais out as 64×64 (2.5×2.5 mm 2 available)  Autozeroed discriminator/pixel w/common threshold/array, programmable test Qinj for each channel, readALL pixels, ADDR0Set, Features of the VIP1 chip: VIP = Vertically Integrated Pixel (64×64 20  m 2 pixel prototype)

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ Floorplan of VIP1 2.5 mm  fully functional matrix of 64×64 pixels including zero suppresed readout, VIP floorplan top view 2.5 mm pads with diode ESD protection for 64×64 pixel matrix 64×64 20  m pitch pixel matrix ramp generator + 5bit gray counter (60  m) + test readAll and readAddr0 + serializer drivers dataClk and injClk (30  m) + analog readout (60  m) time stamp distrib. & readout + generator of column addresses (40  m) generator of row addresses time stamping test structure pads front-end test structures pads sparsification test structure pads Yield problems faced in tests – looks like process problems – problems are not related to TSVs or 3D integration directly but processing of individual layers and charge trapping due to the nature of SOI  single pixel test structures, placed on corresponding layers using internal ring of pads, reduced, or NO ESD protection. Submission Oct. 2006, delivery Nov. 2007, tests accomplished Jun 2008

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ sparsification scheme in VIP1:

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ Tier 3 analog Tier 2 time stamp Tier 1 data sparsification 3D vias distribution of operations between layers in VIP1 38 transistors 72 transistors 65 transistors Counter operates at low speed 30  s/step, ramp 1V/ms Threshold injected after resetting of discriminator (autozeroing)

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ layout view of VIP1 with 3D Design Tool by Micro Magic: bonding pad to detector test pulse injection capacitance HIT release data time stamping FE + discrimination + sampling sparsification

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ tier3 analog layer layout of VIP1

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ tier2tier1 layouts of time stamping and sparsification in VIP1

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/  Very poor yield 1 chip from 2 batches (total 25) allowed assessing results - several chips with open-circuit even on power busses - several chips with shorts (outputs tied to rails, high currents on bias lines) - large leakage currents (mainly dynamic f/f affected), large (up to 100nA) leakage currents in ESD protection diodes - shifts of threshold voltages (up to 200mV) after 3D assembly – Q trapping  Poor current mirror matching (big spread between ratios on different chips)  Poor operation of S/H due to leakages  Discontinuities in readout / wrong values read out Functionality of VIP1 demonstrated in tests  Propagation of readout token  Threshold scan  Input test charge scan  Digital and analog time stamping  Full sparsified data readout  Fixed pattern and temporal noise measurements (not conclusive)   Problems encountered

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ readout token propagation in VIP1 token propagation circuitry is part of sparsification circuitry; if pixel has data to send out high level at the token_in is not transmitted to token_out until the readout of the pixel address, time stamp and signal amplitude is not accomplished. in case of lack of any hits recorded high level propagates through all pixels without interruption propagation of falling edge: NMOS transistors work; faster and less spread between chips propagation of raising edge: PMOS transistors work; slower and more spread between chips  t1  t2  t1  t2 in out

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ pixel-to-pixel threshold dispersion scan in VIP1 A) normal operation conditions, sequence: integrator reset and released, discriminator reset (autozero) and released, threshold application, A) normal operation conditions, sequence: integrator reset and released, discriminator reset (autozero) and released, threshold application,  th =4.9 mV (75 e - )  th =1.6 Mv (25 e - ) Actual threshold voltage is divided by 11 due to capacitive divider Shift due to control signal coupling (?) A B Threshold set at decreasing levels and all pixels over threshold read out using data sparsification scheme B) test operation, integrator reset and held, discriminator reset (autozero) and released, threshold application, B) test operation, integrator reset and held, discriminator reset (autozero) and released, threshold application,

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ Hit pixels in full array as a function of threshold in VIP1 Decreasing threshold Maximum threshold Negative threshold Intermediate threshold

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ injection of test charge to the integrator input VIP1 Preselected pattern of pixels for the injection of signal to the front-end amplifiers; pattern shifted into the matrix, than positive voltage step applied accross the injection capacitance; threshold levels for the discriminator adjusted according to the amplitude of the injected signal Pattern of pixels from the preselected injection pattern that after injection of tests charge reported as hit (grey level represents number of repetition – 8 times injection) 119 pixels injected in this pattern

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ Analog signal response from pixels in test pattern inVIP1 Examine analog response for 119 pixels in preselected pattern using sparsified readout Examine analog response for 119 pixels in preselected pattern using sparsified readout Test capacitor value smaller than expected, however functionality demonstrated B) Mean analog signal level of pixels exceeding the threshold voltage (100ADCu=~35mV), Note: Q inj capacitor = ~0.2fF B) Mean analog signal level of pixels exceeding the threshold voltage (100ADCu=~35mV), Note: Q inj capacitor = ~0.2fF A B A) As level of test charge injected is increased, more pixels exceed the threshold up to reaching total of 119 pixels, A) As level of test charge injected is increased, more pixels exceed the threshold up to reaching total of 119 pixels,

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ time stamping performance in VIP1 (data taken in group of 8 acquisitions) Time stamping studied for 119 pixels in preselected pattern using sparsified readout. Digital time stamping uses inverted Gray code, external ADC used for analog time stamping Time stamping studied for 119 pixels in preselected pattern using sparsified readout. Digital time stamping uses inverted Gray code, external ADC used for analog time stamping B) Analog time stamping suffers from high leakage currents in S/H circuit – needs to be corrected B) Analog time stamping suffers from high leakage currents in S/H circuit – needs to be corrected A B A) The Gray counter is clocked to the tested time stamp value and then charge is injected and the counter value should be sampled in the hit pixels, the readout shows dependence on V DDD, data shows that 118 of 119 pixels have correct time stamp for V DDD =1.4V A) The Gray counter is clocked to the tested time stamp value and then charge is injected and the counter value should be sampled in the hit pixels, the readout shows dependence on V DDD, data shows that 118 of 119 pixels have correct time stamp for V DDD =1.4V

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ VIP1: achievement VIP1: problems VDDD=1.4VVDDD=1.6V VDDD=1.5V  First design of 3D pixel ROIC designed and fabricated,  ubiased measurement: input signal injection, amplification, discrimination, hit storage, time stamping, sparsified readout,  yield problems related to the fabrication technology (3D TSV seem OK),  very high leakage currents (I off corrupting stored signal in S/H), - Current mirror problems due to lack of statistical models, and intrinsic problems of analog design in FDSOI processes, leaking ESD protection diodes,  difficulty in selecting pixels for test pulse injection – missfunction of shift register due to use of dynamic DFF under big leakage currents,  difficulty in selecting pixels for test pulse injection – missfunction of shift register due to use of dynamic DFF under big leakage currents, understood and correction under preparation for the VIP2 run

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ VIP1 had an aggressive design to try to pack all functionalities into a 20×20  m 2 pixel. Extremely long time for delivery of VIP1 circuits from fabrtication >1y!! Exchange of information with other 3DM2 run. Better understandinf of design issues in FDSOI processes (mechanical stresses in transistors, charge trapping, ion flows, thermal isolation etc.) VIP1 had an aggressive design to try to pack all functionalities into a 20×20  m 2 pixel. Extremely long time for delivery of VIP1 circuits from fabrtication >1y!! Exchange of information with other 3DM2 run. Better understandinf of design issues in FDSOI processes (mechanical stresses in transistors, charge trapping, ion flows, thermal isolation etc.) Changes for the VIP2 chip: (48×48 30  m 2 pixel prototype) Submission: Oct. 13th 2008, delivery: summer 2009;  VIP2 will use degraded design rules L min =0.45  m instead of 0.15  m  different power and grounding layout (inter-Tier ground and power ties in each pixel)  redundat vias, width and spacing rules more conservative than MIT-LL  added some diagnostics in serial readout  selectable pull-ups for X- and Y-line flags  7 bits in digital time stamping  redesign of matching sensitive parts (current mirrors)  removal of dynamic logic and increase of strength of output buffers for analog Submission: Oct. 13th 2008, delivery: summer 2009;

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ D integration plans with commercial vendors deep N-wells, MiM capacitors, single poly up to 8 levels of routing metals, variety of transistors (VT optimized) nominal, low power, high performance, low voltage, 8” wafers, reticle 24×32 mm 2 ; Tezzaron vias are very small:  via =1.2  m,  landing_pad =1.7  m, d min =2.5  m Face to Face Bonding Planned submission Spring 2009 (delivery 12 weeks after ) 3D MPW run using Tezzaron/Chartered open for collaborators (France, Italy). Cost-efficient option is considered with only 2 layers of electronics fabricated in the Chartered 0.13 um process, using only one set of masks effective reticle 16×24 mm 2 ) More details given in talk by Bob Patti and discussion session on Fermilab’s 3D MPW on Friday.

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ Conclusions:  First run exploiting 3D-Integration technology with MIT-LL (FDSOI based) process showed feasibility of the design, (to dip a toe in the water)  The architecture proved qualitatively correct operation,  The token based sparsified readout for ILC can be extended for other experiments,  One more submission in MIT-LL is envisaged (submission Oct. 13th 2008), however main effort will be allocated to processes based on the VIA-first principle with bulk CMOS (Tezzaron/Chartered process is extremely appealing),  3D Integration is very attractive for highly granular detector systems, - dedicated EDA tools required – will our community be able to afford?  VIP2 design will be matched with the fabrication of an exteranl detector on HR Si

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ MIRROR C5R3 MIRROR C3R3 ratio 9.1:1 ratio 6.5:1 M. Connell, et all. Impact of Mobile Charge on Matching Sensitivity in SOI Analog Circuits, 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference Built-up mechanical stress – similar to strained Si Built-up of charges (mobile) due to ions flow Examples of problems in FDSOI: designed mirror ratio 10:1

Test Results from the VIP1 Chip, PIXEL_08 09/23-09/26/ Examples of problems in FDSOI: Poor quality of transistor bulk contacts, even using so called H-gate transistors; due to charge accumulation in oxide bulk is floating Self heating of tranistorsdue to poor heat transfer and varying power dissipated on both sides of current mirrors B M Tenbroek, et al., Drain current mismatch in SOI CMOS current mirrors and D/A converters due to localised internal and coupled heating