A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 The PANDA Microvertex Detector: Present Design and Opportunities for 3D Integration Technologies Angelo Rivetti – INFN-Sezione di Torino On behalf of the PANDA MVD group

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 Strong Interaction Studies with Antiprotons Darmstadt, Germany FAIR Facility for Antiproton and Ion Research antiProton ANnihilation at DArmstadt FAIR

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 p Hydrogen Pellet TargetLuminosity Momentum Resolution (  p/p) High luminosity mode 2x10 32 cm -2 s -1 ~10 -4 (stochastic cooling) High resolution mode cm -2 s -1 ~10 -5 (electron cooling < 8 GeV/c) HESR = High Energy Storage Ring Momentum: 1.5 GeV/c - 15 GeV/c p Center of mass energy: √s = 5.5 GeV Antiproton beam

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010  Enhanced forward emission for light targets and distribution over full polar angle for particles momenta below 1 GeV/c.  Combination of colliding beam and fixed target geometry. Simulated particle distribution

A. Rivetti VIPS workshop-Pavia, April 23rd, m 4m Target Spectrometer Surrounds the interaction region. Solenoidal 2T magnet. Forward Spectrometer With a second magnet provides angular coverage for the most forward angles. 1T dipole p The PANDA detector complex

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010  Four barrels: - Two Inner layers: pixels. - Two outer layers: strips.  Six forward disks: - 4 pixels + 2 mixed disks. Read-Out channels and area coverage:  Pixels : 12M channels, 0.14 m 2.  Strips : 200k channels, 0.5 m 2.  Strips are double sided The MVD is the closest detector to the interaction point Primary function: vertexing Additional task: dE/dx for PID The MicroVertex Detector (MVD)

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 Global service routing

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 Pixel detector specifications  Baseline technology : hybrid pixel detectors.  A dedicated front-end chip under development in 0.13  m.  Custom front-end development motivated by high track density (12.3 MHz/cm 2 ) and trigger-less operation.

A. Rivetti VIPS workshop-Pavia, April 23rd, μm Pixel module concept  Geometrical constraints dictates the use of four different module size.  Red circles=parts that might benefit from a 3D approach  Module controller or more cables…

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 Pixel module types  Minimal set of modules to have adequate coverage  Same width, four different lengths

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 Pixel sensors  Baseline choice: epitaxial silicon substrate  p-in-n sensor implementation  epitaxial thickness:  m.  Inert substrate: 50  m.  Alternative: oxygen enriched silicon

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 In each pixel The control logic receives the signal from the comparator and stores the value on the time stamp bus (Gray encoded) at the rising and falling edge in two 12 bit registers. It is present also a 12 bit configuration register. SEU tolerant logic (based on the DICE cell) Each column The readout logic made in a fixed priority scheme to read the timestamps of the pixel cells and to read/write the configuration bits. Master MHz Pixel read-out

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 The analog Front-End generates a pulse whose width is proportional to the charge injected by the sensor. To the digital part ToT Front-end cell Single Pixel Power dissipation of 15 μW from a 1.2 V power supply.

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 Chip prototyping: ToPiX pixel column length: 12.8 mm. 384 pixel cell in four columns: Two folded columns with 128 pixels. Two short column with 32 pixels. Simplified end-of-column logic. Sixteen pixels with wire bonding pad.  ToPix 2.0 is a reduced scale prototype front-end chip for the hybrid pixel sensors.  It has been designed in a CMOS 0.13 μm technology and tested.  The final version of ToPiX will consist of a matrix of 116x110 cells with a pixel size 100 μmx100 μm, thus covering a 1.28 cm 2 active area.

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010  Pulse shape reconstruction using ToT information for different loads at the input. Some experimental results  Americium 60 keV signal in 300 thick  m standard silicon (pixel size 300  m x 300  m)

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010  Signal to noise ratio is limited by parasitics capacitance due the external connections.  Bonding pad+wirebonding+protection diodes.  Still some room to improve the interconnection! Epitaxial sensor 50  m thick, size: 125  m x 325  m Source: Am241,  at 60keV Epitaxial sensor 50  m thick, size: 125  m x 325  m Source: Am241,  at 60keV Tests with an epi-sensor

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 Silicon microstrip

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 Silicon microstrip modules

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 AnalogAnalogDigitalDigital 100 μm μm Do we need extra-dimensions?  Each cell incorporates:  Front-end amplifier  Leakage compensation  5 bit DACs for threshold tuning  Comparator  12 bits configuration register  One register for leading edge  One register for trailing edge  In the present implementation, most of the space reserved to the analog part, but… 3D approach mostly interesting for the pixel part of the MVD

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 DICE cell in 0.13μm technology improves SEU resistance, but not as much as for previous technologies. Improved radiation hardness=more space for the digital part and less for the analog one, with adverse affect on matching Test performed at Laboratori Nazionali Legnaro, using Silicon Radiation (SIRAD) facility Ions used in the beam test: 16 O, 19 F, 28 Si, 35 Cl, 58 Ni, 79 Br Weibull distribution Dice cell SEU performance

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 A two tiers approach?  In the present design only 2/3 (1/2 in the next prototype) of the pixel area is available for the routing of the analog power rails.  No room for local tuning of the feed-back current (no space for DACs and registers)  relatively large ToT spread (12% rms).  Further reduction in density in the next prototype due to the (necessary) migration to a different flavor of the process.  Need to make some compromise on analog performance and on the possibility of adding very desirable features (e.g. protection against “ monster hits ” ). In 1D  Obvious partitioning: One tier for the analog and one for the digital part.  Analog tier: preamplifier, comparator, DACS.  Digital tier: all the rest …  Room for more sophisticated digital processing: no controller chip and less cables!  Room for significant amount of on chip decoupling capacitors … In 2D

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 In summary…  The MVD is a compact but complex detector designed by a relatively small collaboration (compared to LHC detectors).  Rely on well established technologies and minimize custom developments.  In the R&D phase monitoring other developments that may bring significant advantages in term of cost/performance.  3D integration particularly appealing for the hybrid pixel part.  Points that will be of interests  Cheap alternatives to bump bonding  Thinner electronics/sensors  Better front-end electronics (increased functionality due to multi-layers chips)