Introduction to Field Programmable Gate Arrays (FPGAs) EDL Spring 2016 Johns Hopkins University Electrical and Computer Engineering March 2, 2016

What are FPGAs? Field Programmable Gate Array Integrated circuit that can be configured by the user to emulate any digital circuit as long as there are enough resources Array of configurable logic blocks (CLBs) connected through programmable interconnects (switch boxes)

Time line of Programmable Devices

FPGA vs. ASIC (Application-Specific IC)

FPGA Market

FPGA Specifications Block RAM (~1,000-20,000 Kb) Clock speed (~ Mhz) I/O (100s of I/O ports) USB 2.0/3.0 Ethernet PCI-Express Resources (Configurable Logic Blocks) DSP Slices VCCIO supplies

Why Use FPGAs? Reprogrammable! High-Level/Behaviors Hardware Description Language! Logic/Timing Simulation! Parallel, Real-time Processing! Relatively small-size and light-weight! Interface with PC other devices/systems (i.e. Camera)! Prototyping before designing custom chip!

Field Programmable Gate Arrays FPGA Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for SRAM memory chips (Moore’s Law) Huge Density of Logic Block ‘Islands’ 1,000 … 100,000’s in a ‘Sea’ of Interconnects FPGA Architecture

Field Programmable Gate Arrays FPGA

Logic Blocks Logic Functions implemented in Look Up Table LUTs. Flip-Flops. Registers. Clocked Storage elements. Multiplexers (select 1 of N inputs) FPGA Fabric Logic Block

Look Up Tables LUTs LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’. Programmed with outputs of Truth Table Inputs select content of one of the cells as output Configured by re-programmable SRAM memory cells 3 Inputs LUT -> 8 Memory Cells Static Random Access Memory SRAM cells 3 – 6 Inputs Multiplexer MUX

Logic Blocks Larger Logic Functions built up by connecting many Logic Blocks together

Logic Blocks Larger Logic Functions built up by connecting many Logic Blocks together Determined by SRAM cells SRAM cells

Clocked Logic Registers on outputs. CLOCKED storage elements. Synchronous FPGA Logic Design, Pipelined Logic. FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency) FPGA Fabric Clock from Outside world (eg LHC bunch frequency) Special Routing for Clocks

Input Output I/O Getting data in and out Up to > 1,000 I/O “pins” (several 100 MHz)

Input Output I/O Getting data in and out Up to > 1,000 I/O “pins” (several 100 MHz) Special I/O SERIALISERS ~ 10 Gbps transfer rates Optical TRx

Designing Logic with FPGAs Design Capture. High level Description of Logic Design. Graphical descriptions Hardware Description Language (Textual)

Hardware Description Languages Language describing hardware (Engineers call it FIRMWARE) Doesn’t behave like “normal” programming language ‘C/C++’ Describe Logic as collection of Processes operating in Parallel Language Constructs for Synchronous Logic Compiler (Synthesis) Tools recognise certain code constructs and generates appropriate logic Not all constructs can be implemented in FPGA! 2 Popular languages are VHDL, VERILOG Easy to start learning… Hard to master!

VHDL ENTITY Declaration Input Output to Module (STD LOGIC) SIGNALS Declaration WIRES CONCURRENT ASSIGNMENTS CONDITIONAL ASSIGNMENTS => MULTIPLEXERS

VHDL COMPONENT Declaration PROCESS Declaration. CONCURRENT functions. Synchronous Logic.

Designing Logic with FPGAs High level Description of Logic Design Hardware Description Language (Textual) Compile (Synthesis) into NETLIST. Boolean Logic Gates. Target FPGA Device Mapping Routing Bit File for FPGA Logic Simulation Design Flow

Designing Logic with FPGAs High level Description of Logic Design Hardware Description Language (Textual) Compile (Synthesis) into NETLIST. Boolean Logic Gates. Target FPGA Device Mapping Routing Bit File for FPGA Logic Simulation Design Flow

Designing Logic with FPGAs High level Description of Logic Design Hardware Description Language (Textual) Compile (Synthesis) into NETLIST. Boolean Logic Gates. Target FPGA Device Mapping Routing Bit File for FPGA Logic Simulation Design Flow

Configuring an FPGA Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card Configuration takes ~ secs JTAG Testing JTAG Port Programming Bit File

Field Programmable Gate Arrays FPGA Large Complex Functions Re-Programmability, Flexibility. Massively Parallel Architecture Processing many channels simultaneously cf MicroProcessor Fast Turnaround Designs Standard IC Manufacturing Processes. Moore’s Law Mass produced. Inexpensive. Many variants. Sizes. Features. Power Hungry  No Analogue 

FPGA Trends State of Art is 40nm on 300 mm wafers Top of range >500,000 Logic Blocks >1,000 pins (Fine Pitched BGA) Logic Block cost ~ 1$ in 1990 Today < 0.1 cent Problems Power Leakage currents

Sequential vs. Combinational Logic

Sequential Circuits n Combinational Logic (Larger circuits difficult to predict) n Synchronous Logic driven by a CLOCK n Registers, Flip Flops (Memory) Inputs

Sequential Circuits Register CLOCK New Output every clock edge n Combinational Logic (Larger circuits difficult to predict) n Synchronous Logic driven by a CLOCK n Registers, Flip Flops (Memory) Inputs Intermediate EDGES

Sequential Circuits Register CLOCK New Output every clock edge Shift Registers, Pipelines, Finite State Machines … n Combinational Logic (Larger circuits difficult to predict) n Synchronous Logic driven by a CLOCK n Registers, Flip Flops (Memory) Clock Rate determines speed Comb Logic Must meet Timing => Predictable circuits Inputs Intermediate EDGES

FPGA Example 1: Two Wheel Balancing Robot

FPGA Example 2: Face Detection

References The Design Warrior’s Guide to FPGAs Clive Maxfield, Newnes Elsevier VHDL for Logic Synthesis Andrew Rushden, Wiley FPGA manufacturer web sites FPGA Online