EE222 Winter 2013 Sung Mo (Steve) Kang Office BE235 Phone Cell Office BE

References Main: Jan Rabaey, Low Power Design Essentials, Springer, 2009 Others: –A. P. Chandrakasan, et al., Low Power CMOS Digital Design, Kluwer Academic Publishers,1995 –ITRS 2011 ( –R. Sarpeshkar, Ultra Low Power Bioelecrronics, Cambridge Univ. Press, 2010 –F. Catthoor, Unified Low Power Design Flow, Kluwer Academic Publishers, 2000 –Selected articles in journals and conferences

Lecture No.DateSubjectReferenceNote 1Jan 8 (T)IntroductionRby-Ch1 2Jan 10 (Th)Power, Energy BasicsRby-Ch3 3Jan 15 (T)Circuit level power optimizationRby-Ch4 4Jan 17 (Th)Systems level power optimizationRby-Ch5 5Jan 22 (T)continuedRby-Ch5 6Jan 24 (Th)InterconnectsRby-Ch6 7Jan 29 (T)Clock signalingRby-Ch6 8Jan 31 (Th)Low power memoryRby-Ch7 9Feb 5 (T)Low power memoryRby-Ch9 10Feb 7 (Th)Midterm exam 11Feb 12 (T)Low power CASRby-Ch8 12Feb 14 (Th)Low power CASRby-Ch10 13Feb 19 (T)Project proposal presentation 14Feb 21 (Th)Ultra low power/voltage designRby-Ch11 15Feb 26 (T)continued 16Feb 28 (Th)Low power design flowsRby-Ch12 17Mar 5 (T)Continued 18Mar 7 (Th)Project presentation 19Mar 12 (T)Continued 20Mar 14 (Th)Course review

Course Grade Policy Midterm examination 25% Project proposal 25% Final project report 50% –Presentation25% –Report document25%

Guidelines for Course Projects Each team is consisted of 2 members Two members are expected to contribute equally. Project options –Selection of a major milestone paper published in a journal or a conference that addresses low power design of VLSI circuits. –Comprehensive and critical review of the paper. –If possible, propose ways to improve the technical contents. –Both proposals and final presentations will be peer reviewed by other teams.

The Origin of VLSI Systems From Transistor Invention to IC 1956 Nobel Prize, Physics (J. Bardeen, W. Shockley, and W. Brattain) 2000 Nobel Prize, Physics (Jack Kilby) Germanium,1T, 1C, 3R, Oscillator, 0.04 inch X 0.06 inch (Sept. 12, 1958) Dec. 16, 1947 Shockley’s semiconductor device concept (1945) Bardeen and Brattain’s point-junction transistor (1947) Shockley’s junction (sandwich) transistor (1950) Kahng and Attala’s MOSFET (1960) From Transistor to Integrated Circuit

Intel 4004 (‘71), Pentium 3B (‘99), Xeon Nahalem (‘10) Powered by Moore’s Law. 9.5M transistors (2.5um), > 4,000X (2X every 2.3 yrs) 2.3B transistors in 8-core Xeon Nehalem-EX (45nm) 240X over 3B processor (2X every 1.4 yrs) 2,300 transistors (10um)  

Beyond Moore’s Law..

Next Generation Flexible Electronic System. Ref. A. Nathan, et al., Flexible Electronics, Proc. of the IEEE, May 2012

Hierarchy of Limits of Power 5 -System 4 -Circuit 3 -Device 2 -Material 1 -Fundamental

Fundamental Limit Ref. J. D. Meindl,Chapter 2, Low Power Digital CMOS Design, A. P. Chandrasakan & R. W. Brodersen R

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Hierarchy of Limits of Power 5 -System 4 -Circuit 3 -Device 2 -Material 1 -Fundamental

System Level Approach to Minimizing Power LevelParticular tasks SystemPower down, System partitioning AlgorithmComplexity, Locality, Concurrency, Regularity, Data representation ArchitectureConcurrency, Instruction set selection, Signal correlation, Data representation Circuit/LogicLogic optimization, Novel circuits, Transistor sizing, Voltage islands Physical DesignCompact layout, Interconnects TechnologySOI, Advanced packaging

Cray Supercomputer, Interconnects. Complexity of interconnects (Rent’s rule)

Neuromorphic Computing Ref. G. Snider, Memristor and Memristive Systems Symp., Nov Cat scale cortical simulation on LLNL Dawn Blue Gene/P supercomputer with 147,456 CPUs, 144TB main memory (Communications of ACM, July 2011)

Cognitive Computing With Neuroscience, Supercomputing, and Nanotechnology MouseRatCatMonkeyHuman Neurons (B) Synapses (T) Cognitive Computing may lead to  novel learning systems  Non Von Neumann architectures  new programming paradigms  integration, analysis and action on vast amounts of data from many sources at once [ Ref. D. Modha, et al., Communications of ACM, Aug. 2011]

The Missing Link in Constitutive Relations V = R I (Resistor) Q = C V (Capacitor) Φ = L I (Inductor) Φ = f (Q) Φ Q V I V = d/dt Φ d Φ /dt= df(Q)/dt = df(Q)/dQ. dQ/dt V= M I Memristance M=M(Q) I = d/dt Q

Nonvolatile Memristive Memory Nanotechnology enables ultra dense memory S.H. Cho, et. al., Nano Letters, 2009; New York Times, Aug Early 1kB memory based on p-Si/a-Si/Ag by Univ. Michigan HP-Hynix collaboration on next generation memory products  High quality memristive memory chips in a few years  Expected features (compared to FLASH)  Speed: >10x. Power 5X

Nanostore-Based Distributed System with 3D-Stacked Memristors HP- Collocate processors and Memristor memory on chip

Axes of Device Requirements (Memristor)