VHDL 표현방식

Contents Dataflow description Structural description Describing Combinational logic with Dataflow design Structural description Behavioral description

VHDL 표현방식 방법 - 강의순서 데이터 흐름 기술 (Dataflow Descriptions) 부울대수를 이용해서 표현 구조적 기술 (Structural Descriptions) 전체 구조를 단순한 선과 게이트의 연결로 표현 동작 기술 (Behavioral Descriptions) 알고리즘 적인 방식으로 표현 혼합적 기술 (Mixed Descriptions) 위의 3가지방법을 혼합

VHDL 표현방식: Dataflow Description

Dataflow Descriptions 입력과 출력과의 관계를 기술한 부울 대수식을 이용한 설계방식 문장의 순서는 무관하다 병행처리문 (Concurrent Statement)을 주로 사용

Statements 병행(Concurrent) Statement 순차(Sequential Statements) Signal Assignment, Simple Signal Assignment, Conditional Signal Assignment, Selected Process Statement 순차(Sequential Statements) If Statement Case Statement For Loop Statement

CONCURRENCY Concurrent signal assignment statements The term concurrent refers to how the signal assignment statements execute. Statements execute only when associated signals change value. The semantics of concurrent signal assignment statements are designed to mimic the nonprocedural nature of hardware.

CONCURRENCY A VHDL model of a 2-input exclusive OR operation.

CONCURRENCY A VHDL model of a 2-input exclusive OR operation. A signal declaration starts with the reserved keyword signal, followed by the signal name(s) and type. Unlike ports, signals internal to a design entity do not have a mode or a direction of information flow.

CONCURRENCY Concurrent signal assignment statements Each concurrent signal assignment statement executes only when associated signals appearing on the right-hand side change value.

CONCURRENCY Concurrent signal assignment statements The textual order in which concurrent statements appear has no effect on the order in which they execute. The signal assignment statements could have been written as. The input/output signal transform would remain unchanged.

Concurrent statement - Simple Signal Assignment signal_name <= expression; y <= b; 1) b에 변화가 생길 때마다 b의 값이 y에 출력됨 2) Sensitivity List : b y <= a or b; 1) a 나 b에 변화가 생길 때마다 a or b의 값이 y에 출력됨. 2) Sensitivity List : a,b

Example, Dataflow - 2입력 OR Gate Library ieee; Use ieee.std_logic_1164.all; Entity or_2 is port( a, b : in std_logic; y : out std_logic ); end or_2; Architecture dataflow of or_2 is begin y <= a or b; end dataflow;

Concurrent - Conditional Signal Assignment signal <= expression1 WHEN boolean_expression1 ELSE expression2 WHEN boolean_expression2 ELSE expression3; 1) boolean_expression1= 참(True)이면 signal <= expression1이 실행되며, 2) boolean_expression2= 참(True) 이면 signal <= expression2이 실행되며, 3) 위의 2가지 조건이 모두 성립하지않으면 signal <= expression3이 실행된다.

Concurrent - Selected Signal Assignment WITH expression SELECT signal <= expression1 WHEN constant_value1, expression2 WHEN constant_value2, expression3 WHEN constant_value3; 1) expression = constant_value1 이면 signal <= expression1이 실행되며, 2) expresion1 = constant_value2 이면 signal <= expression2이 실행되며, 3) expresion1 = constant_value3 이면 signal <= expression3이 실행된다.

Concurrent – Process Statement Process문의 내부는 sequential statement 복잡한 알고리즘의 구현 시 편리 (Algorithm은 sequential 한 경우가 대부분) Declaration syntax : [Label:] process [( Sensitivity List)] begin Sequential statements; end process [Label];  Sensitivity List에 적혀있는 신호에 변화생길 때 begin과 end process내의 문장을 실행

객체(Object) 값을 가질 수 있는 변수 (object)는 아래의 3가지 종류 Signal (<= 사용) Variable (:= 사용) Constant (:= 사용) The scope of an object is as follows : Objects declared in a package are available to all VHDL descriptions that use package Objects declared in an entity are available to all architecture associated with that entity Objects declared in an architecture are available to all statements in that architecture Objects declared in a process are available only within that process

SIGNAL signal_name : type_name [ :=value]; 객체(Object) - Signals 합성 시에 실제 Wire로 구현 되는 object <= 사용 <= 의 오른쪽에서 왼쪽으로 대입 Process 문 내에서 <= 로 대입되었다면 즉시 수행되는 것이 아니라 end process를 만나야만 수행 됨 Signal의 초기화에는 := 를 사용 Port로 선언하여도 signal임 (port signal) Declaration syntax : 사용 예 signal a, b : std_logic;  선언 a<= ‘1’; b<=‘0’;  Signal a,b에 값 ‘1’, ‘0’을 대입. SIGNAL signal_name : type_name [ :=value];

Example: Dataflow - Andor_2 library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is signal t : std_logic; begin t<=a and b; y<=t or c; end a;

VARIABLE variable_name : type_name [ :=value]; 객체(Object) - Variable Provide convenient mechanism for local storage Scope is within process in which they are declared All variable assignments take place immediately Declaration syntax : 사용 예 variable a, b : std_logic;  선언 a := ‘1’; b :=‘0’;  Variable a,b에 값 ‘1’,’0’을 대입 VARIABLE variable_name : type_name [ :=value];

객체(Object) - Constants Name assigned to a specific value of a type Allow for easy update and readability Declaration syntax : 사용 예 constant bits3_0 : std_logic_vector(2 downto 0) := "000";  선언 y<= bits3_0;  Signal y에 값 “000”을 대입 CONSTANT constant_name : type_name [ :=value];

Dataflow – 4 bits OR gate library ieee; use ieee.std_logic_1164.all; entity or_4bits is port( a, b : in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0) ); end or_4bits; architecture xxx of or_4bits is begin y <= a or b; end xxx; Bus의사용

Dataflow - Half Adder library ieee; Use ieee.std_logic_1164.all; Entity half_add is port( a,b : in std_logic; sum, c_out : out std_logic ); end half_add; Architecture dataflow of half_add is begin sum <= A xor B; c_out <= A and B; end dataflow; 문장의 순서는 무관

Operators Defined precedence levels in decreasing order : Miscellaneous operators -- ** (exponential), abs, not Multiplication operators -- *, /, mod (modulus), rem (remainder) Sign operator -- +,- Addition operators – sll (logical shift left), srl, sla (arithmetic shift left), sra, rol (logical rotate left), ror Relational operators -- =, /=, <, <=, >, >= Logical operators -- AND, OR, NAND, NOR, XOR, XNOR

Attribute Attributes provide information about certain items in VHDL: X’EVENT -- TRUE when there is an event on signal X X’LAST_VALUE -- returns the previous value of signal X Y’HIGH -- returns the highest value in the range of Y X’STABLE(t) -- TRUE when no event has occurred on signal X in the past ‘t’ time

Combinational Logic One or more digital signal inputs One or more digital signal outputs Outputs are only functions of current input values (ideal) plus logic propagation delays i1 Combinational Logic O1 im On

Combinational Logic (cont.) Combinational logic has no memory Outputs are only function of current input combination Nothing is known about past events Repeating a sequence of inputs always gives the same output sequence Sequential logic does have memory Repeating a sequence of inputs can result in an entirely different output sequence

Contents Dataflow design Describing Combinational logic with Dataflow design concurrent signal assignment (<=) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)

Logic Operators Logic operators Logic operators precedence and or nand nor xor not xnor only in VHDL-93 Highest not and or nand nor xor xnor No order precedents Lowest

No Implied Precedence Desired: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; y = (ab + c)d Correct y <= (a and b) or (c and d) ; No order precedents

Arithmetic Operators in VHDL (1) To use basic arithmetic operations involving std_logic_vectors you need to include the following library packages: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; or USE ieee.std_logic_signed.all; Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required.

Arithmetic Operators in VHDL (2) You can use standard +, -, * operators to perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); …… C <= A + B; Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required.

Half Adder The sum can be found using the XOR operation and the carry using the AND operation. S = X  Y, C = XY

Full Adder Full adder adds carry_in as well. The truth table for a full adder is shown at the right.

Full Adder Boolean expression S = m(1,2,4,7) = X’ Y’ Cin + X’ Y Cin’ + X Y’ Cin’ + X Y Cin = X’ (Y’ Cin + Y Cin’) + X (Y’ Cin’ + Y Cin) = X’ (Y  Cin) + X (Y  Cin)’ = X  Y  Cin Cout = m(3,5,6,7) = X’ Y Cin + X Y’ Cin + X Y Cin’ + X Y Cin = (X’ Y + X Y’) Cin + XY(Cin’ + Cin) = (X  Y) Cin + XY

Full Adder

Full Adder, using Half adder

Data-flow VHDL example: Full adder

Data-flow VHDL: Full adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( x : IN STD_LOGIC ; y : IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ; END fulladd ;

Data-flow VHDL: Full adder (2) ARCHITECTURE fulladd_dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; END fulladd_dataflow ;

Ripple Carry Adder Today’s systems employ more efficient adders. Just as we combined half adders to make a full adder, full adders can be connected in series. The carry bit “ripples” from one adder to the next; hence, this configuration is called a ripple-carry adder. ripple: 잔물결, 파문 Today’s systems employ more efficient adders.

Ripple Carry Adder Operation All 2n input bits available at the same time Carries propagate from the FA in position 0 (with inputs x0 and y0) to position i before that position produces correct sum and carry-out bits Carries ripple through all n FAs before we can claim that the sum outputs are correct and may be used in further calculations

Combinational Logic – 4 bits Adder library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity add_4bits_proc is port( a, b : in std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0) ); end add_4bits_proc; architecture a of add_4bits_proc is begin s <= a+b; end a; + 연산자가 사용될 때 꼭 사용. Carry Out이 16이므로 14를 더하면 30이됨. Verify the synthesized RTL logic.

16-bit Unsigned Adder with Cout X Y Cout Cin S 16

VHDL code for a 16-bit Unsigned Adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; END Behavior ;

Contents Describing Combinational logic with Dataflow design concurrent signal assignment conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)

Conditional concurrent signal assignment When - Else target_signal <= value1 when condition1 else value2 when condition2 else . . . valueN-1 when conditionN-1 else valueN; Value N Value N-1 Condition N-1 Condition 2 Condition 1 Value 2 Value 1 Target Signal … Multiplexer

Operators Relational operators Logic and relational operators precedence = /= < <= > >= Highest not = /= < <= > >= and or nand nor xor xnor No order precedents Lowest

Priority of logic and relational operators compare a = bc Incorrect … when a = b and c else … equivalent to … when (a = b) and c else … Correct … when a = (b and c) else … No order precedents

VHDL operators

2-to-1 Multiplexer s f s w w f w 1 1 w 1 1 (a) Graphical symbol w f w 1 1 1 w 1 (a) Graphical symbol (b) Truth table

VHDL code for a 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END Behavior ;

Tri-state Buffer – example (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY tri_state IS PORT ( ena: IN STD_LOGIC; input: IN STD_LOGIC_VECTOR(7 downto 0); output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END tri_state;

Tri-state Buffer – example (2) ARCHITECTURE tri_state_dataflow OF tri_state IS BEGIN output <= input WHEN (ena = ‘0’) ELSE (OTHERS => ‘Z’); END tri_state_dataflow;

4-bit Number Comparator AeqB AgtB 4 B AltB

VHDL code for a 4-bit Unsigned Number Comparator LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;

VHDL code for a 4-bit Signed Number Comparator LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;

Contents Describing Combinational logic with Dataflow design concurrent signal assignment conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)

Selected concurrent signal assignment With–Select-When with choice_expression select target_signal <= expression1 when choices_1, expression2 when choices_2, . . . expressionN when choices_N; expression1 choices_1 expression2 choices_2 target_signal expressionN choices_N choice expression

Allowed formats of choices_k WHEN value WHEN value_1 to value_2 WHEN value_1 | value_2 | .... | value N

Allowed formats of choice_k - example WITH sel SELECT y <= a WHEN "000", b WHEN "011" to "110", c WHEN "001" | "111", d WHEN OTHERS;

4-to-1 Multiplexer s s s s f 1 1 w 00 w w 01 1 1 w f 1 w 10 2 1 w 2 w s s s f 1 1 w 00 w w 01 1 1 w f 1 w 10 2 1 w 2 w 11 3 1 1 w 3 (a) Graphic symbol (b) Truth table

VHDL code for a 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ;

2-to-4 Decoder En w w y y y y 1 1 2 3 w y 1 1 w y 1 1 1 1 1 y 1 1 1 2 1 2 3 w y 1 1 w y 1 1 1 1 1 y 1 1 1 2 y En 1 1 1 1 3 x x (a) Truth table (b) Graphical symbol

VHDL code for a 2-to-4 Decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END Behavior ;

Contents Describing Combinational logic with Dataflow design concurrent signal assignment conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)

For Generate Statement label: FOR identifier IN range GENERATE BEGIN {Concurrent Statements} END GENERATE;

PARITY Generator Example

PARITY: Block Diagram

PARITY: Entity Declaration LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC ); END parity;

PARITY: Block Diagram xor_out(1) xor_out(2) xor_out(3) xor_out(4)

PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: std_logic_vector (6 downto 1); BEGIN xor_out(1) <= parity_in(0) XOR parity_in(1); G2: FOR i IN 1 TO 5 GENERATE xor_out(i+1) <= xor_out(i) XOR parity_in(i+1); end generate G2; parity_out <= xor_out(6) XOR parity_in(7); END parity_dataflow;

PARITY: Block Diagram (2) xor_out(0) xor_out(1) xor_out(2) xor_out(3) xor_out(4) xor_out(5) xor_out(6) xor_out(7)

PARITY: Architecture (2) ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN xor_out(0) <= parity_in(0); G2: FOR i IN 0 TO 6 GENERATE xor_out(i+1) <= xor_out(i) XOR parity_in(i+1); end generate G2; parity_out <= xor_out(7); END parity_dataflow;

실습-03-1 3x8 Decoder를 다음의 VHDL 구문을 이용하여 구현하고 검증하라. 결과로 다음의 세 가지 모두를 제출: VHDL capture RTL Viewer capture Simulation capture 실습-03-1 3x8 Decoder를 다음의 VHDL 구문을 이용하여 구현하고 검증하라. Conditional Signal Assignment (When) Selected Signal Assignment (With-select-when) Case 4x1 MUX를 다음의 VHDL 구문을 이용하여 구현하고 검증하라.

Contents Describing Combinational logic with Block Editor in Quartus II

Design Entry Flow with Quartus II

Drawing logics Create a Block Design File (bdf) Insert gate symbols File > New > Block Diagrams/Schematic File Insert gate symbols Right click > Insert > Symbol

Drawing logics (cont.) Assign pin names Connect double-click move the mouse close to the end-point of a symbol hold the left button and drag or use “Orthogonal Node Tool” button

Simulation of Combinational logic Outputs are only function of current input combination If all the “combinations” of input patterns are examined, then the complete simulation is done. Select a pin, Edit > Value > Clock

Simulation of Combinational logic Set intervals of each inputs properly Save & Simulate

Logic simplifications Consider an automobile buzzer Buzzer = (Key In and Door Open) or (Headlight On and Door Open) B = KD + HD = (K+H)D

Simulation Verify if b_reduced yields the same result.

Compilation Report Verify the reduced equation with Fitter Equation & : AND ! : NOT # : OR $ : XOR

Floorplan Verify the reduced equation with Floorplan

Exercise Simplify X = (ABC’ + B)BC’ by starting with a BDF Verify the result with compilation report & floorplan

Exercise Simplify the equations by starting with a VHDL file X = (AB + (B’+C))’ Y = (AB)’ + (B+C)’ Verify the result with compilation report & floorplan

Entering a Truth Table with VHDL Identify the logic with compilation report & floorplan

실습-03-2 1bit half-adder (HA)를 BDF file로 구현하라. 결과로 다음의 세 가지 모두를 제출: BDF 혹은 VHDL capture RTL Viewer capture Simulation capture 실습-03-2 1bit half-adder (HA)를 BDF file로 구현하라. 1bit full-adder (FA)를 BDF file을 이용하여 구현하고, 수업시간에 제시된 VHDL file로 작성한 회로와 simulation 결과를 비교하라. 4bit Ripple carry FA를 BDF file을 이용하여 구현하고, 수업시간에 제시된 VHDL file로 작성한 회로와 simulation 결과를 비교하라.

실습-03-3 1bit half-adder (HA)를 BDF file로 구현하라. 결과로 다음의 세 가지 모두를 제출: BDF 혹은 VHDL capture RTL Viewer capture Simulation capture 실습-03-3 1bit half-adder (HA)를 BDF file로 구현하라. 1bit full-adder (FA)를 1bit HA를 이용하여 structural VHDL code로 구현하고, dataflow VHDL code로 작성한 회로와 simulation 결과를 비교하라. 4bit Ripple carry FA를 1bit FA를 이용하여 structural VHDL code로 구현하고, dataflow VHDL code로 작성한 회로와 simulation 결과를 비교하라.

Structural Description VHDL 표현방식: Structural Description

Contents Dataflow description Structural description Describing Combinational logic with Dataflow design Structural description Behavioral description

Structural Descriptions 구성 요소 및 연결 자체를 표현 Graphic Editor를 이용한 고전적인 설계방식과 동일. Component( ) 문을 이용하여 선언 Port map( ) 문을 이용하여 핀들을 서로 연결. 위치결합(positional association) Port문 내의 Signal의 위치순서대로 나열 이름결합(named association) Port문 내의 Signal의 위치순서와는 상관없이 ( port문 내의 형식이름=> 실제 이름)의 방식으로 결합.

positional association Structure - Andor_2 and_2.vhd, or_2.vhd는 미리 작성된 상태임. library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is component and_2 port( and_in1, and_in2 : in std_logic; and_out : out std_logic ); end component; component or_2 port( or_in1, or_in2 : in std_logic; or_out : out std_logic ); signal t : std_logic; begin U1 : and_2 port map ( a, b, t ); U2 : or_2 port map (or_in1=> t, or_in2=>c , or_out=>y); end a; And_2선언 and_in1 and_in2 and_out A B T T or_in1 or_out Y Or_2선언 C or_in2 positional association named association

Behavioral Description VHDL 표현방식: Behavioral Description

Behavioral Descriptions 기능적 또는 알고리즘적 표현 고급언어를 사용한 프로그램 작성방법과 유사 Process 사용이 가장 중요한 부분 Process내부에서 sequential statement를 사용

MODELING STYLES Gajski-Khun Y diagram Hardware representations can be thought of as constituting a three-dimensional space: structural, behavioral, and physical.

MODELING STYLES Behavioral and structural representation A behavioral representation or modeling style explicitly defines the input/output function by specifying some sort of mathematical transfer function. A behavioral description defines what a digital design does, but not necessarily how the design is implemented. A structural representation or modeling style describes a digital system by specifying the interconnection of components that comprise the system.

MODELING STYLES – Structural model The difference between behavioral and structural representations can perhaps best be reviewed by an example.

MODELING STYLES – Behavioral model The difference between behavioral and structural representations can perhaps best be reviewed by an example.

MODELING STYLES VHDL modeling style taxonomy Data flow modeling styles use concurrent statements, whereas algorithmic modeling styles use sequential statements.

MODELING STYLES VHDL modeling style taxonomy Sequential statements are principally executed from top to bottom in the sequence in which they are written, recognizing that conditional and iteration constructs can alter this flow of control. The sequence in which concurrent statements are written has no bearing on the order in which the statements execute. The execution of concurrent statements is dependent on certain data conditions, hence the term data flow.

MODELING STYLES Three sample signal assignment statements If the statements are sequential signal assignment statements, they execute from top to bottom in the textual order listed. If the statements are concurrent signal assignment statements, the textual listing of the statements has no bearing on the order in which they execute.

Process - Recap Process문의 내부는 sequential statement 복잡한 알고리즘의 구현 시 편리 (Algorithm은 sequential 한 경우가 대부분) Declaration syntax : [Label:] process [( Sensitivity List)] begin Sequential statements; end process [Label];  Sensitivity List에 적혀있는 신호에 변화생길 때 begin과 end process내의 문장을 실행 Optional

Sequential Statement: IF IF expression1 THEN statement1-1; statement1-2; ELSIF expression2 THEN statement2-1; statement2-2; ELSE statement3-1; statement3-2; END IF; 1) expression1 = 참(True)이면 statement1-1, state1-2가 실행, 2) expression2 = 참(True) 이면 statement2-1, state2-2가 실행, 3) 위의 2가지 조건 모두 성립하지않으면 statement3-1, state3-2가 실행,

Behavioral – Sequential Statement (IF) library ieee; use ieee.std_logic_1164.all; entity mux21_if_proc is port( a,b : in std_logic; s : in std_logic; y : out std_logic); end mux21_if_proc; architecture proc of mux21_if_proc is begin process(a,b,s) if( s='0') then y<=a; else y<=b; end if; end process; end proc; a, b,s 에 변화생길 때 실행 마지막 조건은 else로 처리해야 함.

Sequential Statement: Case CASE expression IS WHEN constant_value1 => statement1-1; statement1-2; WHEN constant_value2 => statement2-1; statement2-2; WHEN OTHERS => statement3-1; statement3-2; END CASE; 1) expression1 = constant_value1 이면 statement1-1, state1-2가 실행, 2) expression1 = constant_value1 이면 statement2-1, state2-2가 실행, 3) 위의 2가지 조건 모두 성립하지않으면 statement3-1, state3-2가 실행,

Behavioral – Sequential Statement (case) library ieee; use ieee.std_logic_1164.all; entity mux21_case_proc is port( a,b : in std_logic; s : in std_logic; y : out std_logic); end mux21_case_proc; architecture proc of mux21_case_proc is begin process(a,b,s) case s is when '0' => y<= a; when others => y<= b; end case; end process; end proc; 마지막 조건은 others로 처리해야 함.

Sequential – For Statement loop_label: FOR index_variable IN range LOOP statement1; statement2; END LOOP loop_label; index_variable 의 값을 변해가면서 statement1, statement2를 반복적으로 실행. 아래의 (a), (b)는 모두 같은 표현임. Range는 downto, to의 2가지형태임. loop_Start: FOR i IN 0 to 3 LOOP y(i) <= a(i) and b(i); END LOOP loop_Start; (a) y(0) <= a(0) and b(0); y(1) <= a(1) and b(1); y(2) <= a(2) and b(2); y(3) <= a(3) and b(3); (b)

Behavioral – Signal vs. Variable library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is Begin process(a,b,c) variable t : std_logic; begin t :=a and b; y<=t or c; end process; end a; library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is signal t : std_logic; Begin process(a,b,c,t) begin t<=a and b; y<=t or c; end process; end a; 선언되는 위치차이 Sensitivity List차이 2 1 1 Signal t는 Process문이 끝나는 순간에 일괄적으로 값이 할당. 2 3 Variable은 대입 즉시 값 할당.

Behavioral – Signal vs. Variable library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a: in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is Begin process(a) variable t : std_logic; begin t :=a; y<=t; end process; end a; library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a: in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is signal t : std_logic; Begin process(a,t) begin t<=a; y<=t; end process; end a;

참고문헌 PERRY, VHDL 4/E : PROGRAMMING BY EXAMPLE . FLOYD, DIGITAL FUNDAMENTALS WITH VHDL . ARMSTRONG,GRAY, VHDL DESIGN REPRESENTATION & SYNTHESIS. SKHILL, VHDL FOR PROGRAMMABLE LOGIC . PELLERIN, VHDL MADE EASY. LEE, VHDL CODING & LOGIC SYNTHESIS WITH SYNOPSYS.