1 WA105 General Meeting CERN, 21/9/2015 Status of charge readout analog and digital FE Dario Autiero, L. Balleyguier, E.Bechetoille, D.Caiulo, B.Carlus, L. Chaussard, Y. Declais, T. Dupasquier, S. Galymov, C.Girerd, J. Marteau, H.Mathez, E. Pennacchio IPNL Lyon

2 ASIC cryogenic amplifiers with double slope gain Adapted to LEM dynamics like previous version 1200 fC single slope Larger gain up in the few mip region, kink point point at 10 mip and reduced gain by a factor 3 up to 40 mips max dynamic range  Received beginning of January 2015  Replace feedback capacitor of the preamplifier with a MOS capacitance which changes the C value above a certain threshold voltage (gain ~ 1/C). Selectable double time constant in discharge or single one with diode +resistor to keep constant RC Double slope implementation (starting from previous ASIC version):

3 ASIC cryogenic FE The double-slope version has some imperfections: -The value of the MOSCAP capacitance physically resulting in the circuit implementation is smaller than the one in the submitted design (150 pF vs 250 pf) due to process dependence -The smaller value of Cf plus a parasitic capacitance effect on the feedback resistor branch was introducing a dependence of the response on Cdet (lower signal by increasing Cdet and longer peaking time) Response and peaking time dependence on Cdet We have produced a single-slope version in 2013 (up to 1200 fC dynamic range) and a double-slope version at the end of 2014  Both versions have noise within specifications and work correctly at cold: Noise measurements as a function of Cdet and various temperatures. At cold around 100k: ENC=3.3*Cdet+234 e-  1200 e- at 300 pF 0 pF 250pF 62.5pF 125pF 187.5pF ENC Warm Cold Double-slope response measurement at Cdet=250 pF on 6 different chips (curves very close)

4 Simulation at cold of recently submitted version: Kink at 400 fC ~13 mip with LEM gain = 20 ~log regime up to 1200 fC Double-slope design improved and new circuit submitted (will be available in December) -Design of MOSCAP less process dependent -Removal of parasitic capacitance on feedback resistor branch -Better differential driver integrated from another IN2P3 development Circuit produced as a test batch (25 units) with purchase option for already produced 600 units (entire WA105 production) if the tests on the 25 ordered units confirm expectations In stock unpurchased production of single-slope chip (up to 100 units, 1600 channels) is also available  New chip in production, decide in January which chips stock to buy for the massive deployment in WA105: perfected double-slope or single-slope

5 RC discharge Double opposite diodes components preferred for capacitance and performance

6 uTCA crates Readout in groups of 640 channels/chimney 64 channels AMC digitization ( MHz, 12 bits) card prototype based on Bittware S4AM 10 GbE output WA105 uTCA charge readout architecture  640 channels per chimney/uTCA crate  10 AMC/crate  64 channels/AMC

7 DAQ timing-trigger integration CC 1CC 2 CC 12PMC CC 6 CC GbE links + 2 spares Bittware card 1Bittware card GbE links + 1 spares Meinberg GPS White Rabbit GrandMaster switch WR slave MCH mezzanine WR slave trigger board Time Beam window NIM signal every 20 s Beam Trigger counter NIM signal ~ a few 100 Hz Charge readout Light readout WR Clock + time + triggers Digitized data Time Data processing PC 1Data processing PC 2 Trigger PC Cosmics counters

8 White Rabbit based Time/trigger distribution scheme WR Grand Master SWITCH Meinberg GPS MASTER CLOCK µTCA Shelf WR slave µTCA Shelf WR slave µTCA Shelf WR slave µTCA Shelf WR slave Clock + time + trigger data on uTCA backplane Clock + Time AMC GbE AMC PC WR slave Trigger board No need to develop analog clock distribution system and microTCA receiver cards Beam counters/large area cosmic counters trigger board also in WR standard  generates trigger timestamps transmitted on WR network Light readout DAQ uTCA  generates trigger timestamps transmitted on WR network Development of the WR slave as MCH mezzanine from a commercial WR node Sub-ns sync accuracy Time and Trigger distribution Light readout uTCA crate (generates light triggers)

9  WR Grand Master Switch WRS-3/18 18 SFP fiber cages, 1GbE Supports connections up to 10 km distance Connected to Meimberg GPS as time source  PC time-tagging trigger board SPEC carrier board+ Fine Delay FMC Can time-stamp with 1ns accuracy beam trigger signals or external large area scintillator counters  Trigger time-stamps data are transmitted over the WR network to the microTCA MCH  WR-LEN (White rabbit Light Embedded Node)  WR slave node cards basis of WA105 development for a MCH WR uTCA mezzanine SPEC FMC PCIe carrier V4FMC Fine Delay 1 ns 4 channels Commercial components for the WR network:  Received WR components at IPNL  Set up test system of slave card, defined scheme to use slave card I/O to propagate signals to uTCA backplane  Additional IPNL engineer L. Balleyguier working of the firmware of the WR slave card Test-bench with Meimberg + switch + slave node

Trigger counter uTCA crate of LRO PMTs For light readout Crate with NIM logic Spill signal (cable) PC with WR time stamping card WR Time stamps: Beam trigger Start of spill External cosmic trigger Calibration pulses External trigger plane for cosmics WR switch Light readout (LRO) WR link x12 Charge readout WR links Light

 Definition of LRO digitization requirements in collaboration with SB, reported in LRO digitization talk of this afternoon During spills we need a continuous digitization in the +-4 ms around the trigger time of the light (the light signal is instantaneous and has the real arrival time of the cosmics) Sampling can be coarse up to 400 ns to correlate to charge readout  Example: sum 16 samples at 40MHz to get an effective 2.5 MHz sampling like for the charge readout The LRO card has to know spill/out of spill Out of spill it can define a light triggers when n PMTs are over a certain threshold and transmit it over the WR

12 AMC digitization card Board characteristics – µTCA standard (double width, full height) – 64 input channels (2V / 14 bits / 2.5 Msps to 20 Msps) – Control through MCH 1GbE backplane link port 0/1 – Data transmission through 10GbE backplane and MCH 10GbE SW – Local buffer dual port memory (512K + 256K 18 bits) samples per channel. (or more if necessary to be confirmed )

13 Data acquisition demonstrator (available since January) Based on µTCA AMC S4AM from Bittware FMC mezzanine board with 64 ADC channels Control through GbE Data transmission through 10GbE AMC S4AM 64 ADC ch FMC mezzanine

14

15

16

17 From the S4AM demonstrator to the production of the final AMC card Tests with the S4AM demostrator card completed by June: ADC section fully operational, DAQ firmware validated for 10 GbE  Since June design activities moved to design of the final card: Main design aspects of the card and components defined, conceptual design frozen Tests with the S4AM kit and simulations have shown that the final FPGA dimensioning is not possible with the FPGAs originally foreseen but a higher category FPGA (ALTERA Cyclone V GX) is needed. This is due to I/O limitations in the implementation of the LVDS links to the ADCs. The change to a higher class, more expensive, FPGA implies some overcosts. New FPGA used at 25% of logic elements and 65% of I/O. Other components: DPRAM memories, ADCs, service circuitry components for uTCA confirmed, tenders being launched for production purchase Card design being finalized on the basis of the conceptual design. The final circuit design should become available by end of November for submission  Production by the end of the year of a first batch of 10 cards to perform the final tests before massive production and also have immediately one crate available for the 3x1  In parallel purchase of the frozen components for the massive production with available money (1/3 of needed money)  Massive production to be launched in February after final tests by using pre-purchased components and getting the missing 2/3 of funds from IN2P3 at the beginning of 2016

FPGA Cyclone V GX ADCs AD9257 Total 64 ch. Connector 68p VHDCI Local oscillator (125 MHz) Connecteur AMC Clock Generator DPRAM IDT70V33 39 DPRAM IDT70V33 39 µTCA MMC MAXV Flash configuration 20 MHz 40 MHz MHz 1 Gbe 10 Gbe 125 MHz POWER supplies POWER supplies Conceptual layout, basic firmware and main components frozen  card routing to be completed

19 Production organization for 6x6x6 The money made available by IN2P3 by the end of 2015 corresponds to ~1/3 of what foreseen in the MOU to handle to entire FE/DAQ production (possibility of a loan from CERN or other partners not accepted) Use this money to handle the production of the ASIC, a pre-production batch of 10 digitization cards (8 in standby for mounting to check routing on the first two) and to buy some main frozen components for the mass production (ADCs, FPGAs, Memories, etc …)  Have a first batch to be able to work on 3x1 by February, launch in February the main electronics production with the complement from 2016 money ASIC: Improved version of double-slope ASIC submitted. Circuits available for tests in December, already produced the circuits for the full production with purchase option if final tests O.K. Single slope version working fine  backup option. Already enough circuits to equip the 3x1 have been produced as «unpurchased stock spares » They can be purchased in January (up to 100 chips, 1600 channels), if necessary, and a full production to complete for the 6x6 can be launched as well in January. uTCA digitization AMCs: final design to be completed by November, submission of pre-batch of 10 AMCs, buy some components with available money for massive production (tenders to be launched this week). Massive production to be launched in February with additional 2016 money Timing WR: system components purchased, buy additional extra 12 slave nodes in 2016, adapt to a carrier for uTCA, simpler scheme than MCH

20 Conclusions:  Both versions of cryogenic ASIC working within noise specifications at cold. Double- slope version resubmitted with some corrections to achieve final performance. Massive production with purchase option. Single slope version has enough spares already produced to equip 3x1 can be a backup option. On the basis of the tests on latest submission in January decide for which one of the two versions to go for massive deployment.  Design phase of AMC digitization cards completed on the basis of S4AM prototype, components frozen. Change of FPGA class to be purchased for final card needed for I/O limitations. Final card routing in progress, to be completed by end of November. Submission of a pre-batch of 10 cards by the end of Massive purchase of some main frozen components with available money. Massive production to be launched in February after checks and with money complement from 2015 budget  Timing/trigger scheme defined with white rabbit. Main components of the chain purchased, the system can provide what we need. Firmware work on slave node card in progress in order to transfer to the backplane the appropriate trigger signals.