BITS Pilani Pilani Campus Pawan Sharma ES C263 Microprocessor Programming and Interfacing

BITS Pilani, Pilani Campus Text Book: Barry B Brey, The Intel Microprocessors Architecture, Programming and Interfacing.Prentice Hall. Eigth edition J P Misra, et.al., Lab Manual for Microprocessor Programming and Interfacing. EDD Notes. Reference book: Douglas V Hall, Microprocessor and Interfacing, TMH, Second Edition. Overview

BITS Pilani, Pilani Campus  Microprocessor history  Disk Organisation  8086 Hardware  Assembly Language Programming  Interface to peripheral devices Course Layout

BITS Pilani, Pilani Campus Objectives: The course will provide knowledge to build and program microprocessor based systems. Microprocessor architecture and programming Architecture of microprocessor based systems Grading: Mid-sem test—40 marks (open book), Comprehensive Exam---80 marks (open book), design assignment & viva marks

BITS Pilani, Pilani Campus Microprocessor-based systems are electrical systems consisting of microprocessors, memories, I/O units, and other peripherals. Microprocessors are the brains of the systems. Microprocessors access memories and other units through buses. The operations of microprocessors are controlled by instructions stored in memories What are microprocessor-based systems? Memory Output units Input units Bus Microprocessor Control unit Datapath ALU Reg.

BITS Pilani, Pilani Campus Evolution of Computers and Intel Microprocessors

BITS Pilani, Pilani Campus 1ENIAC 1.Electronic Numerical Integrator And Computer 2.Eckert and Mauchy of University of Pennsylvania 3.Trajectory tables for weapons 4.Started 1943 and Finished Too late for war effort Used until 1955 First Generation – Vacuum tubes

BITS Pilani, Pilani Campus 1.Decimal (not binary) 2.20 accumulators of 10 digits 3.Programmed manually by switches 4.18,000 vacuum tubes 5.30 tons 6.15,000 square feet kW power consumption 8.5,000 additions per second ENIAC features

BITS Pilani, Pilani Campus Electronic Numerical Integrator and Computer (ENIAC)Computer

BITS Pilani, Pilani Campus

1945: The "Bug" is Born

BITS Pilani, Pilani Campus 1.Von Neumann - Stored Program concept - Main memory storing both programs and data 2.ALU operating on binary data 3.Control unit interpreting instructions from memory and executing 4.Input and output equipment operated by control unit IAS computer - Princeton University's Institute of Advanced Studies (1952)

BITS Pilani, Pilani Campus

The von Neumann model consists of five major components: (1) input unit; (2) output unit; (3) arithmetic logic unit; (4) memory unit; (5) control unit.

BITS Pilani, Pilani Campus Transistor was Invented in 1947 at Bell Labs by William Shockley et al. –Replaced vacuum tubes –Smaller –Cheaper –Less heat dissipation –Solid State device –Made from Silicon (Sand) Second Generation - Transistor

BITS Pilani, Pilani Campus Third Generation – IC (1958) From Magnetic Memory to Semiconductor Memory

BITS Pilani, Pilani Campus 1.CPU in a chip - microprocessor 1.Personal computers 1.IBM PC 2.Apple 3.commodore 1.Intel (integrated electronics) Fourth generation - VLSI

BITS Pilani, Pilani Campus First microprocessor (1971) For Busicom calculator Characteristics 10  m process 2300 transistors 400 – 800 kHz 4-bit word size 16-pin DIP package Masks hand cut from Rubylith Drawn with color pencils 1 metal, 1 poly (jumpers) Diagonal lines (!) 4004

BITS Pilani, Pilani Campus 8-bit follow-on (1972) Characteristics 10  m process 3500 transistors 500 – 800 kHz 8-bit word size 18-pin DIP package 8008

BITS Pilani, Pilani Campus 16-bit address bus (1974) Used in Altair computer (early hobbyist PC) Characteristics 6  m process 4500 transistors 2 MHz 8-bit word size 40-pin DIP package 8080

BITS Pilani, Pilani Campus 16-bit processor (1978-9) IBM PC and PC XT Revolutionary products Introduced x86 ISA Characteristics 3  m process 29k transistors 5-10 MHz 16-bit word size 40-pin DIP package Microcode ROM 8086 / 8088

BITS Pilani, Pilani Campus Virtual memory (1982) IBM PC AT Characteristics 1.5  m process 134k transistors 6-12 MHz 16-bit word size 68-pin PGA Regular datapaths and ROMs 80286

BITS Pilani, Pilani Campus 32-bit processor (1985) Modern x86 ISA Characteristics  m process 275k transistors MHz 32-bit word size 100-pin PGA 32-bit datapath, microcode ROM, synthesized control 80386

BITS Pilani, Pilani Campus Pipelining (1989) Floating point unit 8 KB cache Characteristics  m process 1.2M transistors MHz 32-bit word size 168-pin PGA Cache, Integer datapath, FPU, microcode, synthesized control 80486

BITS Pilani, Pilani Campus Superscalar (1993) 2 instructions per cycle Separate 8KB I$ & D$ Characteristics  m process 3.2M transistors MHz 32-bit word size 296-pin PGA Caches, datapath, FPU, control Pentium

BITS Pilani, Pilani Campus Dynamic execution (1995-9) 3 micro-ops / cycle Out of order execution KB I$ & D$ Multimedia instructions PIII adds 256+ KB L2$ Characteristics  m process 5.5M-28M transistors MHz 32-bit word size MCM / SECC Pentium Pro / II / III

BITS Pilani, Pilani Campus Deep pipeline (2001) Very fast clock KB L2$ Characteristics 180 – 90 nm process M transistors GHz 32-bit word size 478-pin PGA Units start to become invisible on this scale Pentium 4

BITS Pilani, Pilani Campus Moore’s Law

BITS Pilani, Pilani Campus Intel Core Architecture

BITS Pilani, Pilani Campus 32 bits 64-bit bus 1.5 GHz42,000, Pentium 4 32 bits 64-bit bus 450 MHz9,500, Pentium III 32 bits 64-bit bus 233MHz7,500, Pentium II 32 bits 64-bit bus 60MHz3,100, Pentium 32 bits25MHz1,200, bits16MHz275, bits6MHz134, bits5MHz29, bits2MHz6, Data width Clock speed TransistorsDateName The Evolution of Microprocessors