ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.

Slides:

Advertisements

Similar presentations

Sumitha Ajith Saicharan Bandarupalli Mahesh Borgaonkar.

Advertisements

Aug Data/Clock Synchronization Fourteen ways to fool your synchronizer Ginosar, R.; Asynchronous Circuits and Systems, Proceedings. Ninth International.

Asynchronous Counter with MSI Gates

Laboratory for SoC design TEMPUS meeting Niš,

CSE 378 Computer Hardware Design Prof. Richard E. Haskell – –Tel: –Web site: Follow.

Stop Watch Sean Hicks Dongpu Jin ELEC 307 Project 2 Instructor: Alvaro Pinto April/12/2011.

XILINX ISE 9.1/9.2. To Get Familiar with the Environment How to start an FPGA project How to target your design to particular type of FPGA How to describe.

Performed by: Lin Ilia Khinich Fanny Instructor: Fiksman Eugene המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון - מכון טכנולוגי.

COE Labs Objectives and Benefits. General Objectives 1.Students’ training using state-of-the-art facilities through course labs 2.Enable world-class research.

Page 1 Simplifying MSO-based debug of designs with Xilinx FPGAs.

Controls Lab Interface Improvement Project #06508Faculty Advisors: Dr. A. Mathew and Dr. D. Phillips Project Objectives This work focused on the improvement.

Technion Digital Lab Project Xilinx ML310 board based on VirtexII-PRO programmable device Students: Tsimerman Igor Firdman Leonid Firdman Leonid.

EE296 Working with the FPGA’s. (Field Programmable gate array) Team name: Altezza Team members: Richard Phomsouvanh (FPGA expert) Jason Leong (VHDL expert)

ECE 699: Lecture 2 ZYNQ Design Flow.

CSE 378 Computer Hardware Design Prof. Richard E. Haskell – –Tel: –Web site: Follow.

Technion Digital Lab Project Performance evaluation of Virtex-II-Pro embedded solution of Xilinx Students: Tsimerman Igor Firdman Leonid Firdman.

Implementation of DSP Algorithm on SoC. Characterization presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompany engineer : Emilia Burlak.

Introduction to FPGA’s FPGA (Field Programmable Gate Array) –ASIC chips provide the highest performance, but can only perform the function they were designed.

Pulse-modulated Radar Display Processor on a Chip Talal Darwich Center for Advanced Computer Studies University of Louisiana at Lafayette.

W.Skulski Phobos Workshop April /2003 Firmware & software development Digital Pulse Processor DDC-8 (Universal Trigger Module) Wojtek Skulski University.

LSU 10/22/2004Serial I/O1 Programming Unit, Lecture 5.

Chapter 5 Engineering Tools for Electrical and Computer Engineers.

Introduction to FPGA AVI SINGH. Prerequisites Digital Circuit Design - Logic Gates, FlipFlops, Counters, Mux-Demux Familiarity with a procedural programming.

Matrix Multiplication on FPGA Final presentation One semester – winter 2014/15 By : Dana Abergel and Alex Fonariov Supervisor : Mony Orbach High Speed.

Status Report Atsushi Nukariya. FPGA training course ・ I solved 15 problems which are proposed by Uchida-san. ・ I used above circuit board. FPGA.

A comprehensive method for the evaluation of the sensitivity to SEUs of FPGA-based applications A comprehensive method for the evaluation of the sensitivity.

A flexible FGPA based Data Acquisition Module for a High Resolution PET Camera Abdelkader Bousselham, Attila Hidvégi, Clyde Robson, Peter Ojala and Christian.

1 Keyboard Controller Design By Tamas Kasza Digital System Design 2 (ECE 5572) Summer 2003 A Project Proposal for.

Spring Introduction  Today’s tutorial focuses on introducing you to Xilinx ISE and Modelsim.  These tools are used for Verilog Coding Simulation.

High-Level Interconnect Architectures for FPGAs Nick Barrow-Williams.

PRESENTED BY OUSSAMA SEKKAT Self-Healing Mixed-Signal Baseband Processor for Cognitive Radios.

FPGA (Field Programmable Gate Array): CLBs, Slices, and LUTs Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side.

VHDL Project Specification Naser Mohammadzadeh. Schedule  due date: Tir 18 th 2.

ECE 449: Computer Design Lab Coordinator: Kris Gaj TAs: Tuesday session: Pawel Chodowiec Thursday session: Nghi Nguyen.

An Embedded True Random Number Generator for FPGAs Bebek, Jerry Paul Kohlbrenner Lockheed Martin 3201 Jermantown Road Fairfax, VA 22030, USA

Characterization presentation Winter Performed by: Tomer Michaeli Liav Cohen Supervisor: Shlomo Beer Gingold In collaboration.

© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU DSP Design Flow System Generator for DSP.

Test Management Provides a rich and configurable global web platform for implementing a software development life cycle process with collaboration.

A. Steininger / TU Wien 1 Advanced Digital Design Organisation.

Coincidence Detector on SOPC Coincidence Detector on SOPC Final Presentation Presenting: Roee Bar & Gabi Klein Instructor:Ina Rivkin Technion – Israel.

Preliminary Design of FONT4 Digital ILC Feedback System Hamid Dabiri khah Queen Mary, University of London 30/05/2005.

Final Presentation Final Presentation OFDM implementation and performance test Performed by: Tomer Ben Oz Ariel Shleifer Guided by: Mony Orbach Duration:

Upgrade to the Read-Out Driver for ATLAS Silicon Detectors Atlas Wisconsin/LBNL Group John Joseph March 21 st 2007 ATLAS Pixel B-Layer Upgrade Workshop.

LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGA Project Guide: Smt. Latha Dept of E & C JSSATE, Bangalore. From: N GURURAJ M-Tech,

ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis.

Technion – Israel Institute of Technology Department of Electrical Engineering Spring 2009 Instructor Amit Berman Students Evgeny Hahamovich Yaakov Aharon.

UClinux console (HyperTerminal) Memec V2MB1000 prototyping board running uClinux on embedded Xilinx® MicroBlaze™ processor Development system with Xilinx.

Structuring Experimenting Esmée Bertens Tim de Ridder Herman de Vos /Department of Mechanical Engineering Systems Engineering Group Masters Team Project.

Introduction to Labs Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

DDRIII BASED GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD PART B PRESENTATION STUDENTS: OLEG KORENEV EUGENE REZNIK SUPERVISOR: ROLF HILGENDORF 1 Semester:

Introduction ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

Lab Environment and Miniproject Assignment Spring 2009 ECE554 Digital Engineering Laboratory.

Internal Logic Analyzer Characterization presentation By: Moran Katz and Zvika Pery Mentor: Moshe Porian Dual-semester project Spring 2012.

Real-Time System-On-A-Chip Emulation.  Introduction  Describing SOC Designs  System-Level Design Flow  SOC Implemantation Paths-Emulation and.

I 2 C FOR SENSORS IN THE DOM Nestor Institute Koutsoumpos Vasileios - Nestor Institute 1.

FIGURES FOR CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN

ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and Isim. Using Seven-Segment Displays, Buttons, and Switches.

Performed by: Tomer Michaeli Liav Cohen Instructor: Shlomo Beer Gingold Cooperated with: המעבדה למערכות ספרתיות מהירות High speed digital.

1 Introduction to Engineering Spring 2007 Lecture 18: Digital Tools 2.

Prototyping SoC-based Gate Drive Logic for Power Convertors by Generating code from Simulink models. Researchers Rounak Siddaiah, Graduate Student-University.

FPGA-Based Smart Meter Interface

NI 9605 board Ethernet Cable Host PC LabVIEW GUI FPGA chip Processor

Xilinx ChipScope Pro Overview

Figure 1 PC Emulation System Display Memory [Embedded SOC Software]

Multi-Agent Testbed for Emerging Power Systems

Future Year Scheduling

CS170 Computer Organization and Architecture I

Engineering Tools for Electrical and Computer Engineers

Advanced Digital Design

♪ Embedded System Design: Synthesizing Music Using Programmable Logic

Presentation transcript:

ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis

WHAT YOU GET FROM US A working late transition detector Implementation of [PS13] But without the case separation Nevertheless all counters are present But hard wired to measure the overall count only Python based PC software Automates the measurement Prints a CSV trace to standard out

ENVIRONMENT Virtex-4 FPGA Board is lend to students Design software: ISE webpack can be freely downloaded (after Xilinx) Includes all necessary design tools PC software Python program for collection of CSV traces Analysis with program of choice (Excel, Python, MATLAB,...)

YOUR TASKS Implement the case separation from [PS13] Measure three different clock duty cycles (+25, +50 and +75 steps) Analyze your measurements Calculate the different TAU values (master and slave, if applicable) for all cases and simulation runs Estimate T0 (if applicable) for all cases and simulation runs Plot each case in a separate plot and visualize the above calculated parameters Comparison plots of All cases in a single run All runs for a single case

EXAMPLE TRACE

EXAMPLE COMPARISON

REFERENCES PS13 - T. Polzer and A. Steininger - An Approach for Efficient Metastability Characterization of FPGAs through the Designer -19th International Symposium on Asynchronous Circuits and Systems, 2013

ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis