EE222 Winter 2013 Lecture 11 Sung Mo (Steve) Kang Low power design flow CAD Apache Cadence EPFL

Lecture No.DateSubjectReferenceNote 1Jan 8 (T)IntroductionRby-Ch1 2Jan 10 (Th)Power, Energy BasicsRby-Ch3 3Jan 15 (T)Circuit level power optimizationRby-Ch4 4Jan 17 (Th)Systems level power optimizationRby-Ch5 5Jan 22 (T)continuedRby-Ch5 6Jan 24 (Th)Interconnects and clock signalingRby-Ch6 7Jan 29 (T)Memristive computingInvited lecture-Dr. S. Shin 8Jan 31 (Th)Midterm exam 9Feb 5 (T)Low power CASRby-Ch8 10Feb 7 (Th)Low power CASRbt-Ch10 11Feb 12 (T)Ultra low power/voltage designRby-Ch11 12Feb 14 (Th)Ultra low power/CAD, Sub Vth circuitsRby-Ch 11, etc. 13Feb 19 (T)Project proposal presentation 14Feb 21 (Th)High Bandwidth I/O for memoryInvited lecture-Prof. C. Kim! 15Feb 26 (T)Ultra low power ADC CircuitsSarpeshkar Ch15 16Feb 28 (Th)Low power RF TelemetrySarpeshkar Ch18 17Mar 5 (T)Low power design flowsRby-Ch12 & F. Catthoor 18Mar 7 (Th)Project presentation 19Mar 12 (T)Continued 20Mar 14 (Th)Course review

EE222 Peer Review Form Winter 2013 Quarter Steve Kang Evaluator Name______________________________ Title of Presentation____________________________________ Date _______________________________________ CategoryScore (0-5 highest) 1Relevance to Low Power IC Design 2Perceived significance and clarity of presentation 3Quality of the work proposed/accomplished OverallWhat is your overall evaluation score (0-5, where 5 is the highest)

EE222 Winter Projects 1.Resonant Clock for Energy Recovery 2.Interconnects for CMOS Topology 3.Asynchronous Design Techniques 4.Low Power Computer Architecture 5.Memristive Memory

F2: VLSI Power-Management Techniques: Principles and Applications Organizer/Chair: Leland Chang, IBM, Yorktown Heights, NY Co-Chair: Shannon Morton, NVIDIA, Bristol, United Kingdom Committee: Ken Chang, Xilinx, San Jose, CA Leland Chang, IBM, Yorktown Heights, NY Jin-Man Han, Samsung, Hwasung, Korea Piero Malcovati, University of Pavia, Pavia, Italy Shannon Morton, NVIDIA, Bristol, United Kingdom Vladimir Stojanovic, MIT, Cambridge, MA Across the spectrum of microelectronics applications, power management is critical to enabling of power-efficient products. This Forum will provide practicing circuit designers with a summary of power-management techniques, including perspectives from a wide range of product applications, and an outlook for the future in the context of coming challenges. The first four speakers in this Forum will present the general principles in development today, including power-gating and state-retention modes, PLL/DLL techniques for dynamic frequency scaling, integrated voltage regulators for dynamic voltage scaling, and low-power signaling. In the second half, four speakers representing different industry perspectives, including microprocessors, consumer electronics, microcontrollers and mobile, and DRAM, will utilize practical case studies to detail current usage of power-management techniques and speculate on future trends.

08:20 Introduction Leland Chang, IBM, Yorktown Heights, NY 08:30 Advanced Power-Gating and State-Retention Approaches to Leakage-Power Reduction David Flynn, ARM, Cambridge, United Kingdom 09:20 Clocking Techniques for Dynamic Frequency Scaling Jaeha Kim, Seoul National University, Seoul, Korea 10:10 Break 10:35 Dynamic Voltage Scaling Using On-Chip Voltage Regulation Gu-Yeon Wei, Harvard University, Cambridge, MA 11:25 Power Management in High-Performance I/O Jared Zerbe, Rambus, Sunnyvale, CA 12:15 Lunch 13:20 Fine-Grain Power Management in Microprocessors Vivek De, Intel, Hillsboro, OR 14:10 A Key to Power Management for Digital Consumer Applications Yukihiro Urakawa, Toshiba, Kawasaki, Japan 15:00 Break 15:20 Embedded Power-Management Solutions for Ultra-Low-Power SoCs: Implementation Examples of Radio-Connected Microcontrollers and Mobile-Application Microprocessors Frédéric Hasbani, ST Microelectronics, Crolles, France 16:10 Power-Management Techniques in DRAM Design Sangho Shin, Samsung, Hwasung, Korea

Apache Ultra-Low-Power Methodology addresses today’s complex SOCs: RTL Power Analysis, Debug, and Reduction with PowerArtist: Understand and lower power consumption early, efficiently, and effectively with a powerful graphical environment Reduce clock, memory and datapath power with a range of sequential and combinational automatic techniques Make reliable early power-related design decisions with power-smart, physical- aware PowerArtist Calibrator and Estimator (PACE™) models Track power via regressions throughout the design flow RTL to Physical Power Integrity with PowerArtist RTL Power Model (RPM™) Perform early power grid and package prototyping before chip layout is available Increase power integrity sign-off coverage with worst case power cycles rapidly identified from millions of RTL vectors Seamless model-based flow from PowerArtist to RedHawk™ with RPM, and RedHawk to Sentinel™ with Chip Power Model (CPM™)

RTL POWER REGRESSION RTL POWER TRADEOFF ANALYSIS RTL POWER DEBUG AND REDUCTION RTL POWER MODEL EARLY POWER INTEGRITY & PACKAGE ANALYSIS DESIGN IMPLEMENTATION POWER INTEGRITY SIGNOFF APACHE DESIGN SOLUTIONS- ULTRA LOW POWER FLOW

Impact of technology scaling on ultra-low-power systems Armin Tajalli Ecole Polytechnique Fédérale de Lausanne (EPFL) Microelectronic Systems Laboratory (LSM) December 2009 LSM Group Meeting █ULTRA LOW POWER CIRCUIT AND SYSTEM DESIGN

Motivation Technology scaling – Main issues in ULP: Variation / reliability Leakage / Energy consumption – Goals: Study / analyze Explore limitations Propose design methodology Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Main Concerns in ULP Primary issue: energy consumption Secondary issue: delay/speed Figure of merit: PDP, ED, etc Optimal point – V DD(OPT) – E min Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Subthreshold Operation V DD(OPT) : – depends on activity rate – depends on device parameters (V T, DIBL, n, etc) – is generally less than V T Subthreshold operation: – Variability – Leakage Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Reliability Metric: Noise Margin Limited by: – DC gain – VDD – Variability Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

NM Precise value of NM: Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Noise Margin Drain current in subthreshold: Maximize NM ( X C = V DD /2 ): Calculate VTC : Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Noise Margin G ain drop due to DIBL NM including variation Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Noise Margin Comparing to transistor-level simulations Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Noise Margin NM vs I ON /I OFF Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Noise Margin Positive NM: Equivalently: Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

High-VT Lower V DD – Less dynamic and static dissipation [+] – Less noise margin [-] – Sensitive to variation [-] High-V T – Less static power dissipation [+] – No effect on noise margin [+] – Exponential increase in delay [-] Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Noise Margin Positive NM: –Conclusion: size scales proportional to A VT Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Energy Consumption Including: – activity rate – leakage – logic depth Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Energy Consumption Critical activity rate: Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Discussion – Scaling rules in subthreshold/ULP are different – A combination of size/V DD scaling is required to keep energy consumption very low – Critical device parameters in ULP: DIBL, I ON /I OFF, S – Use high-V T instead of lower V DD if delay is not a concern ! Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

Case Study Example 1. Impact of technology scaling on ultra-low-power systems ● Armin Tajalli ● EPFL LSM ● December /18

SUBTHRESHOLD SOURCE-COUPLED CIRCUITS