Students: Inna Sigal and Yuval Bar-Tal Supervisor: Tsachi Martsiano Spring 2015

This project will present a method for accelerating simulation on FPGA by using SW model on FPGA’s embedded CPU.

 Long RTL Simulations on PC have some limitations:  Long runtime.  Huge database.  The amount of cycles per run is limited.

 The industries known solutions are:  Bought emulation platforms, such as: Palladium, EVE, Veloce.  Usually data is driven from external source, such as: PCI, ETH, USB, etc.  Usually results are being transmitted to external source for comparison with SW/Matlab algorithms

 We propose a method, in which the data will be driven and checked internally:  A SW model will be generated via the FPGA’s internal CPU.  Data will be generated by RTL data generator, or by the 2nd CPU on the FPGA.  Results will be checked inside the FPGA.

FFS0FFS0 FFS1FFS1 FFS2FFS2 FFS3FFS3 FFS4FFS4 FFs5FFs5 FFS6FFS6 FFS7FFS7 FFS8FFS *** * * 26 to to CO C1 C4 C2 C3 Data outData out  We are concentrating on FIR as a test case.

SW Model HW Implementation Simulate Both to bit match using DPI Build FPGA+CPU+CHIPSCOPE env Run tests on FPGA

 SW model – C.  HW implementation – Verilog  HW simulation – ModelSim with DPI-C  Emulator – Xilinx ZedBoard [with ARM dual core CPU]  FPGA/CPU SW – Eclipse  FPGA tool – Xilinx SDK, and Vivado.  Testing – Xilinx ChipScope.

 DPI stands for Direct Programming Interface.  Allows us to call C/Cpp functions from the HW simulation [in our case ModelSim]  We will use DPI to call the “algorithm” functions coded in C, and run the HW design besides the “algorithm”.

CPU Data gen

CPU Data gen

CPU Data gen

CPU Data gen

CPU Data gen

CPU Controller The idea: Polling GPIO registers in order to synchronize between the CPU and PL

CPU Controller The idea: Polling GPIO registers in order to synchronize between the CPU and PL

CPU Controller The idea: Polling GPIO registers in order to synchronize between the CPU and PL

PL CPU DUT results Software model results

Data gen

FFS0FFS0 FFS1FFS1 FFS2FFS2 FFS3FFS3 FFS4FFS4 F s5 FFS6FFS6 FFS7FFS7 FFS8FFS *** * * 26 to to CO C1 C4 C2 C3 Da t a ou t

FFS0FFS0 FFS1FFS1 FFS2FFS2 FFS3FFS3 FFS4FFS4 F s5 FFS6FFS6 FFS7FFS7 FFS8FFS *** * * 26 to to CO C1 C4 C2 C3 Da t a ou t

FFS0FFS0 FFS1FFS1 FFS2FFS2 FFS3FFS3 FFS4FFS4 F s5 FFS6FFS6 FFS7FFS7 FFS8FFS *** * * 26 to to CO C1 C4 C2 C3 Da t a ou t

SW Model HW Implementation Simulate Both to bit match using DPI Build FPGA+CPU+CHIPSCOPE env Run tests on FPGA

SW Model HW Implementation Simulate Both to bit match using DPI Build FPGA+CPU+CHIPSCOPE env Run tests on FPGA

SW Model HW Implementation Simulate Both to bit match using DPI Build FPGA+CPU+CHIPSCOPE env Run tests on FPGA

SW Model HW Implementation Simulate Both to bit match using DPI Build FPGA+CPU+CHIPSCOPE env Run tests on FPGA

Build FPGA+CPU+CHIPSCOPE env SW Model HW Implementation Simulate Both to bit match using DPI Run tests on FPGA

Build FPGA+CPU+CHIPSCOPE env Run tests on FPGA SW Model HW Implementation Simulate Both to bit match using DPI