1 Etat d’avancement de la conception des Blocs FEI4 CPPM, Université de la méditerranée, CNRS/IN2P3, Marseille, France

2 16/11/2009 Réunion Electronique pour SLHC Outline  Introduction  Memory block for the global configuration : CNFGREG  Temperature sensor : TEMPSENS  10 bit Global ADC : GADC  Variants :  Pixel configuration  Low Power discriminator  Additional blocs ?

3 16/11/2009 Réunion Electronique pour SLHC CNFGMEM  Layout : DRC and LVS ok  Post layout simulations in order to estimate the influence of long wires capacitances on the time response.  Buffers are ok  Output amplifier not needed  Next step :  From the review : Only one error out for the whole bloc (instead of 1 per word)  Voltage shifters: 1.2 V to 1.5 V  Schematic ok and layout have to be done  Error In pull up for the first stage have to be done  Verilog modelling for the memory cell  Corners simulations  Estimate timing parameters for write and read cycles  1 week of work to freeze the design 16 rows by 32 colomns All inputs and outputs pins are on the top side Block dimensions : 900µm × 360µm 5:32 decoder Memory cell

4 16/11/2009 Réunion Electronique pour SLHC TEMPSENS  The schematic is ok  Layout : DRC and LVS not yet completed  Next step :  Finalise the layout  Post layout simulations in order to estimate the influence of long wires resistances on the current value  Corners simulations  3-4 weeks of work to finalize the design

5 16/11/2009 Réunion Electronique pour SLHC GADC  Schematic  The comparator not yet figed  Global simulation : Ok  Layout  DAC and MUX ok  SAR control logic : in progress  Comparator : have to be done  Next step :  SAR design  Comparator design  Corner and mismatch simulations for the GADC  Global layout  Post layout simulations  2 weeks for the SAR  2 weeks for the comparator  2 weeks for the Global layout

6 16/11/2009 Réunion Electronique pour SLHC Pixel Configuration  Layout in progress  2 weeks to finalize the bloc

7 16/11/2009 Réunion Electronique pour SLHC Low power discriminator  Layout ok  To be done when the pixel array is fully designed  Additional Vdddiscri …  1 week to implement the bloc in the pixel

8 16/11/2009 Réunion Electronique pour SLHC Planning CNFGMEMMohsine TEMPSENSFabrice GDAC SARLaurent CompMohsine GlobalLaurent Pixel confDenis

9 16/11/2009 Réunion Electronique pour SLHC Additional blocs ?  An analog MUX and output analog buffer :  The MUX should have 32 analog voltage inputs 5-bit address input  single analog output with a buffer capable of driving a passive oscilloscope probe.

10 16/11/2009 Réunion Electronique pour SLHC Additional blocs ?  Temperature dependent current source (or voltage source if easier).  The temperature dependence should have a programmable slope (4 bits or more).  In the case of a V source the slope should be adjustable between +5mV/C and -5mV/C  In the case of a current source between +1%/C and -1%/C  An op-amp is already designed and available  Temperature-stable voltage and current references are also available

11 16/11/2009 Réunion Electronique pour SLHC Additional blocs ?  Temperature dependent current source (or voltage source if easier).  The temperature dependence should have a programmable slope (4 bits or more).  In the case of a V source the slope should be adjustable between +5mV/C and -5mV/C  In the case of a current source between +1%/C and -1%/C  An op-amp is already designed and available  Temperature-stable voltage and current references are also available