High-Speed Serial Interface Test in Production Assure Device Interoperability In Real-World Environments

About GuideTech Specializing in Precision Timing for Semiconductor Test and Scientific Lab Communities since 1988 Core Technologies  Continuous Time Interval Analyzer (CTIA)  Fast Datacom Analysis Software (DCA)  High Channel Count, Parallel Architecture Targeting production test of high-speed serial interfaces

Sample Applications Semiconductor Test PLL & Spread Spectrum Clocks Source Synchronous Bus Embedded-Clock Serial I/O Scientific Analysis Jet Engine Rotation/Vibration Atomic Clock Drift & Particle decay GuideTech Keeps the Planet’s time! US Master Clock at the US Naval Observatory ASE test floor

The Need for Speed PCs move to high-speed serial buses in  80% - 2.5Gbps PCI-Express  100% - 1.5Gbps Serial-ATA  20% - Gigabit Ethernet But test quality is not yet assured! 1 Morgan Stanley – Sep 22, 2003 Semiconductor Capital Equipment Industry Research ControllerDeviceControllerDevice 16 < 200Mbps ControllerDeviceControllerDevice 2 pairs of differential >800Mbps

400MHz +/-150ps Digital Synchronous ATE ATE Performance Gap Year DUT 1.6G Source Synchronous Flat Panel DVI Digital Video Interface Spread Spectrum PLL Clocks To lower EMI emissions of cell phones & consumer devices GuideTech has been filling the gap since 2001 Performance 1.2G - 3.2G Embedded-clock Serial (e.g. XAUI, SATA, FC & PCI-Express) High Speed High Accuracy High Throughput Asynchronous test

A New Test Paradigm Scope Slow, Statistical Averaging Gross test of Total Jitter & Eye CTIA & DCA Fast, Frequency Domain Analysis Per-edge timing analysis

Continuous TIA Technology Continuous Timestamps  Record edge timing & event count relative to (T0,E0) Multiple measurement types derived from same data set All measurement channels reference same (T0,E0) Powerful Pulse Selection Arming  “Walk” measurements through data patterns  Skip pulses to measure specific pulses E0 E1 E2 E3 T0 T1 T2 T3 T4 T5 T6 Meas # Event # Timestamps 1 E1 T1, T2 2 E2 T3, T4 3 E3 T5, T6 CTIA Local Memory Meas # Event # Pulse Width 1 E1 T2 – T1 2 E2 T4 – T3 3 E3 T6 – T5 Real-Time DSP PW E2

Non-Continuous TIA Drawbacks Non-Continuous TIA based on simple Time Counter technology  Random, absolute measure of time intervals  No inherent reference to common (T0,E0)  Relies heavily on Statistical Analysis methods Time interval #1 Time Interval #2 Requires physical Pattern Marker for highest accuracy  Pattern match adds test time to synchronize to patterns  Pattern match unreliable in presence of large jitter Requires repeating SEARCH for one-shot measurements  PLL Lock Time

CTIA Single-Shot Capability Test PLL & Spread Spectrum Clocks in production One-shot  Frequency  Modulation  Lock Time  Jitter No arming Picosecond accuracy In milliseconds 8 in parallel Up to 64 channels

CTIA Frequency Domain Analysis CTIA time correlation enables plot of time interval error (TIE) Time (us) TIE  t (ps )  t 0  t 1  t 2  t 3  t 4  t 5  t 6 AMPLITUDE FREQ FFT of the TIE plot provides the amplitude and frequency of sinusoidal jitter/modulation f jitter Auto Correlation Plot Of Sinusoidal Jitter

ATE Digital Compare Method ATE Digital Compare Method – Requires Match Mode to position strobes Functional Test of Non-deterministic Signals Non-continuous TIA Non-continuous TIA – Requires Marker to locate desired bit location Continuous TIA Continuous TIA – Reconstructs repeating signals with ‘Virtual Marker’ Match Match Pattern Marker PM selects the next desired pulse to measure T0 T1 T2 T3 E0 E2 E5 E GT4000

CTIA “Virtual Marker” Edge isolation & reconstruction of non-deterministic bit patterns  Known Bit Pattern & UI  Selectable Bit Event Count  Correlated CTIA Timestamps (Tn,En) More reliable than a physical pattern marker in high jitter signals Reduces test times to milliseconds for…  Per-edge jitter analysis  Asynchronous pattern verification

Serial Interface Test in Production Many test options  High-$peed ATE  BERT  Scope  Jitter Analyzers Few cost-effective approaches  Loopback  On-chip DFT/BIST But ‘no test’ is not an option anymore…

Serial I/O Loopback Test Benefits Benefits  Low-cost vs expensive ATE pin electronics  Addresses asynchronous issue with ATE TX diff RX diff Drawbacks Drawbacks  Gross Functional Test only  Does not insure device interoperability in real-world system environments

Assure Real-World Performance BER helps insure real-world performance but is too slow for production High-throughput jitter analysis can estimate BER in production Near-end  TX Jitter Analysis Predicts far-end jitter degradation after TX signal is subjected to system connectors, switches and PCB traces Far-end TX diff RX diff CTIA measures TX jitter in loopback path

Random Jitter Causes of Random Jitter Causes of Random Jitter  Thermal noise  Transistor current fluctuation ‘shot’ noise  Flicker noise (1/f noise) Random Jitter is a contributing factor to Bit Error Rate DJ QxRJ BER SJ Eye BER Q = BER

RJ is important for fast BER estimation Measuring Bit Error Rate on a BERT can take hours or days Quickly determine Total Jitter for a BER of Jitter p-p = ( Q x RJ RMS ) + DJ Q = BER Due to the large Q multiplication factor, RJ measurements must not be contaminated by PJ and DDJ components Gaussian RJ RJ contaminated by PJ RJ contaminated by DDJ Probability Density Functions (PDF) of jittering edge timing QxRJ BER

Data-Dependent Jitter is Important Most PHY-layer I/O failures are DDJ-related Most PHY-layer I/O failures are DDJ-related Causes of DDJ Causes of DDJ  Bandwidth limitations in signal path Frequency dependent Pattern dependent  Output driver faults  Duty cycle distortion  Rise/fall times  Packaging

CTIA DataCom Jitter Analysis  GuideTech DCA Provides: Data Pattern Verification Random Jitter (RJ) Data-Dependent Jitter (DDJ) Periodic Jitter (PJ) Total Jitter (TJ) Bit Error Rate (BER) Eye Width Continuous TIA technology enables fast and accurate quality assurance

CTIA RJ Immune to PJ CTIA continuous timestamping enables isolation of the RJ noise floor by removal of PJ frequency components in the FFT spectrum and DDJ using virtual marker 0.1MHz 10MHz 50MHz Jitter Amplitude (UI) 1UI 0.5UI 0.1UI Remove Spread Spectrum Clock Modulation Remove other periodic jitter Remaining Noise Floor (Random RMS Jitter) Statistical (Curve fit) methods are prone to estimation errors depending on the PDF shape PDF showing RJ contaminated by PJ & DDJ

RJ Immunity to DDJ CTIA continuous timestamps act as a ‘virtual’ marker  Isolate edges  Remove DDJ offset before performing FFT for RJ analysis P 1N 2P 2N 3P 3N Count IDEAL Edge-6 location T0 DDJ offset

CTIA vs. ‘double-delta’ method P1N1P2N2P3N3P4N4P5N5P6N6 CTIA measures edge shifts independently on each data bit  Produces highly repeatable DDJ results per-edge  Avoids inaccuracies of statistical double-delta methods* Continuous TIA * Reference: Fibre Channel MJS document Section & Inherent DDJ inaccuracies of double-delta method* Non-Continuous TIA

10x Throughput with Picosecond DCA Correlation to Scope DCA correlates to Agilent within picoseconds DCA test time is less than 1 sec vs. 10 sec on scope (K28.5)

DCA Fast Jitter Separation Select DCA test time Select DCA test time  Pattern length  PJ resolution  PJ ON/OFF  RJ precision Test PCI Express in 1 second (including pattern verify) } RJ precision PJ – OFF (RJ, DDJ & TJ only) PJ – ON (RJ, DDJ, PJ, TJ) } PJ resolution K28.5 PCIe PRBS bit 32,767 bits Compliance Pattern Test Time (sec) 10s 5s 1s250ms Pattern Length (bits)

The Value of Jitter Test Jitter test saves money Jitter test saves money  Test Escapes Field Returns RMA failure analysis Lost Business  Yield Loss Failing good devices  Time-to-Market Delays Long characterization-to-production correlation time Unprepared to debug unexpected process variation at final test

CTIA Provides the Missing Pieces Introducing theGT4000 Continuous TIA Booth # 1420 Test Asynchronous signals Test Asynchronous signals High Throughput “Virtual Marker” High Throughput “Virtual Marker” Repeatable Jitter Analysis Repeatable Jitter Analysis 64 Single-ended / 32 Differential 64 Single-ended / 32 Differential

High-Speed Serial Interface Test in Production Assure Device Interoperability In Real-World Environments 2004