ESDG Mtg 15th April CMS-FED Production FEDv1 Productions Jan 2003 : 2 boards. Working. June 2003 : 3.

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Presentation transcript:

ESDG Mtg 15th April CMS-FED Production FEDv1 Productions Jan 2003 : 2 boards. Working. June 2003 : 3 boards. Working. Oct 2003 : 6 boards. Major problems. “Unusable” Mar 2004 : 6 boards. Working. DDi. (3 at CERN ; 1 in Pisa)  Basic board functions on FEDv1 verified.  Baseline Firmware (4 FPGA designs) now implemented and tested.  Minimal changes for FEDv2 boards in progress. Aim to make couple of FEDv2 boards by October.  EU Tender Process (£2M+ contract) CMS Silicon Tracker Readout. 10 M 100 kHz L1 => 500 x 9U boards installed < Q2/2006 collaborating closely with Imperial College

ESDG Mtg 15th April FED Block Diagram  9U VME64x Form Factor  Modularity matches Opto Links  ~ 25K strips / FED  8 x Front-End “units”  OptoRx/Digitisation/Cluster Finding  Back-End module / Event Builder / buffer  VME module / Configuration  Power module  NB No links between FEDs.  Other Interfaces:  TTC : Clk / L1 / BX  DAQ : Fast Readout Link  TCS : Busy & Throttle  VME : Control & Monitoring  JTAG : Test & Configuration TTCrx Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Units x 8 CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface 8 x FE-FPGA Cluster Finder TTC Trigger Temp Monitor JTAG 9U VME64x FPGA 24 x Delay- FPGA ADC Clocks BE-FPGA Event Builder VME-FPGA Boot & Configure

ESDG Mtg 15th April Firmware Status Clocks Data Serial Comms VME LINK VME Bus VME System ACE System ACE EPROM TTCrx QDR Write QDRs QDR Read Serial Comms Headers TTC chanA VME LinkRegs S-LINK Clocks Data Serial Comms Scope Mode Header Mode FIFOs Input Regs Serial Comms Scope Mode Header Mode Output Input Regs Opto Rx DAC Opto Rx DAC DELAY FPGA x 3 x 8 FE FPGA x 8 BE FPGA VME FPGA ADC Under Simulation Under Test on FED Controls Data Readout Control Throttle TCS Input Cluster Mode Ed->Saeed Saeed Saeed Ed->Saeed Ed, John Saeed, Ivan Chan B I2C “Working” on FED External Devices Temp 15th March 2004 To be Implemented Spy Clocks FEDv2

ESDG Mtg 15th April Summary FEDv1 6 more FEDv1’s just passed commissioning tests. Tests at (CERN, Imperial & RAL) proceeding well. Aim is to finalise changes for FEDv2 in April. Design FEDv2 Implement design changes in April/May Manufacture couple of boards in summer. Manufacture Looking for a one stop shop solution. Presently evaluating possible candidates for large FED production (also outside UK). Proposal document for test at Assembly plant. Learning fast about operation of processes and facilities. EU Tender Investigating EU procedures. Take advantage of present RAL EU framework tender.