Test Generation for Designs with Multiple Clocks Xijiang LinSudhakar M. Reddy Mentor Graphics Corp SW Boeckman Rd. Wilsonville, OR ECE Department University of Iowa Iowa City, IA 52246

2 Outline  Introduction  Existing test generation approaches for designs with multiple clocks  Proposed method  Experimental results  Conclusions

3 Introduction  Scan based structural tests are an effective and efficient way to reduce test generation cost.  Test application time is proportional to the number of test patterns to be applied.  To reduce test application cost, it is desirable to apply test sets of smaller size while maintaining desired test coverage.  Methods to reduce test pattern count during test generation:  Dynamic compaction.  Static compaction.

4 Design with Multiple Clocks  In today’s VLSI designs, multiple clocks have been extensively used to improve system performance.  Clock structure can be utilized to reduce the test pattern count by allowing pulsing more than one clock during capture.  To avoid unknown clock skew, interacting clocks are typically not pulsed simultaneously during test generation.  A pair of clocks is said to be interacting if data captured by one clock can impact the data captured by another clock.

5 Example of Interacting Clocks DFF1 clk1 DFF2 clk2 a b  1 DFF1 clk1 DFF2 clk2 a b  1  ? ? Not Safe!!! Safe

6 Existing Approaches  Approaches to generate test patterns without having clock skew problem:  Clock domain analysis.  Pulse the non-interacting clocks simultaneously during capture.  Clock concatenation.  Apply different clocks sequentially.  Mixture of the above two approaches. scan_en clk1 clk2 scan_en clk1 clk2

7 Clock Domain Analysis  Identify interacting clocks based on structural analysis and create a clock interaction table. Iclk1clk2clk3clk4 clk10100 clk21001 clk30001 clk40110  Apply clock interacting table to dynamically group non- interacting clocks and pulse them simultaneously during test generation.  For example: {clk1, clk3}, {clk1, clk4}

8 Clock Concatenation  Pulse interacting clocks sequentially to reduce test pattern count. clk2clk1 a b si se c d DFF1 DFF x 1 s-a-0 1 x x  Since test data volume is dominated by scan data and test application time is dominated by scan loading time, the cost of storing and applying extra cycles between scan loading and unloading can be negligible

9 Motivation  Typically, the number of state elements in the inter-clock domains is much less than the total number of state elements controlled by the interacting clocks.  Majority of faults are not observed at the state elements in the inter-clock domain.  Allow to pulse interacting clocks to reduce test pattern count:  When pulsing interacting clocks simultaneously, one can mask out the state elements in the inter-clock domain.  Mask out operation means assigning capture value X to a state element.

10 Motivation (Cont’d) s-a-0 s-a-1 clk2 clk1 DFF1DFF2 DFF3DFF4 DFF5DFF6 g1 g2 g (1) (0) (X) Mask Out

11 Overview of Test Generation Flow  Preprocess:  Identify state elements in inter-clock domain.  While target fault list is not empty:  Generate test cube for a primary target fault.  Do dynamic compaction by expanding test cube:  Allow to pulse interacting clocks while targeting additional faults.  The state elements in the inter-clock domain are not masked out.  Fault simulate generated test and drop detected faults:  During good machine simulation, mask out state elements in inter-clock domain.

12 Identify State Elements in Inter-Clock Domain  For each pair of interacting clocks, structural analysis is used to identify two set of state elements:  IS: State elements in inter-clock domain.  DS: State elements driving the state elements in IS. clk1clk2 IS1 DS1 clk2clk1 IS2 DS2

13 Example clk1 DFF1DFF2DFF3 clk2 a b cf d e g h IS(clk1, clk2)={DFF2, DFF3} DS(clk1, clk2)={DFF1, DFF2}

14 Identify Mask-out State Elements  When pulsing interacting clocks simultaneously, it is unnecessary to mask out all the interacting state elements. DFF1 clk1 DFF2 clk2 a b c d e (1) No Mask DFF1 clk1 DFF2 clk2 a b c d e (0) (1) Mask Out

15 Identify Masked-out State Elements Dynamically During Simulation  Step 1: Simulate next time frame k in a test pattern by ignoring clock skew problem.  Step 2: If interacting clocks are pulsed simultaneously in k, change current state of a driving state element S i in DS to logic value X when:  Current state and the next state at S i simulated from Step 1 is different.  Step 3: Resimulate time frame k.  Step 4: If a state element in IS has its next state value changed to X, it is a masked-out state element.

16 Example DFF1clk1DFF2clk2 a b c d e (0) (1) DFF1 clk1 DFF2 clk2 a b c d e X 1 0X 0 DS={DFF1}, IS={DFF2} (0) (X) Mask Out

17 One Iteration of Simulation Is Not Enough d clk1 DFF1DFF2DFF3 clk2 a b cf e g h (0) (1) d clk1 DFF1DFF2DFF3 clk2 a b cf e g h 0 1 X X (0) (X)(X) (X)(X) (1) Mask Out If clk1 arrives DFF3 after clk2 arrives DFF2, we cannot trust the capture value at DFF3. DS={DFF1, DFF2} IS={DFF2, DFF3} ???

18 Must Simulate Iteratively d clk1 DFF1DFF2DFF3 clk2 a b cf e g h 0 1 X X (0) (X) (1) Mask Out (0) (X) (X)(X) Mask Out  1st simulation iteration: d clk1 DFF1DFF2DFF3 clk2 a b cf e g h 0 1 X X 1 X X 0  2nd simulation iteration: Mask Out

19 Unsuccessfully Tested Faults  When fault simulating the test pattern generated by the test generator for a target fault, the fault may be undetected by the fault simulator:  Test generator ignores the clock skew problem by allowing interacting clocks pulse simultaneously.  Some state elements in the inter-clock domain will be masked out during fault simulation.  If the target fault is observed at masked out state element, the fault becomes undetected by fault simulator.  Goal: Test generation should not lose test coverage.

20 Two-Phase ATPG  Phase 1: Test generator can generate test patterns pulsing interacting clocks simultaneously by assuming that there is no interaction among clocks.  State elements in the inter-clock domain are masked out during fault simulation.  Phase 2: Faults unsuccessfully detected after phase 1 are targeted again by disabling pulsing of interacting clocks.  Clock domain analysis is used.

21 Observations in ATPG Phase 1  Observation 1: If a large percentage of interacting state elements exist for an interacting clock pair:  Mask out operation during fault simulation will make significant number of detectable faults become unsuccessfully tested when pulsing this clock pair simultaneously.  Observation 2: When a large number of detectable faults become unsuccessfully tested in ATPG phase 1, significant number of additional test patterns will be generated in ATPG phase 2.

22 Reduce the Impact of Unsuccessfully Tested Faults on Pattern Count  Strategy 1: Allow pulsing an interacting clock pair only if:  Strategy 2: Monitor the number of unsuccessfully tested faults during test generation and stop ATPG phase 1 if:

23 Circuits under Experimental Circuit# Gates# Scan Cells# Clocks# Clock Domains ckt1313.5K20.2K115 ckt2466.1K34.6K215 ckt3743.8K66.6K2410 ckt4912.7K56.4K217 ckt52.45M138.1K248 ckt62.37M160.1K3410

24 ATPG Setups for Comparison  Restriction off: All clocks are treated as non- interacting clocks.  Give a low bound for test pattern count.  Clock domain analysis: Allow to pulse non- interacting clocks simultaneously.  Proposed method:   =0.05 and β=   =1.0 and β=0.0075

25 Test Generation Results for Stuck-at Faults Circuitckt1ckt2ckt3ckt4ckt5ckt6 Pattern Count Restriction Off Clock Domain

26 Test Generation Results for Broad-side Transition Faults Circuitckt1ckt2ckt3ckt4ckt5ckt6 Pattern Count Restriction Off Clock Domain

27 Conclusions  We proposed a two-phase test generation approach to reduce test patterns for designs with multiple clocks:  Allowing pulsing interacting clocks simultaneously.  Mask out state elements in the inter-clock domain to avoid unknown clock skew problem.  Significant test pattern count reduction is achieved for industrial designs when comparing with clock domain analysis.

28 Thank you