EE141 Timing Issues 1 Chapter 10 Timing Issues Rev /11/2003

EE141 Timing Issues 2 Synchronous Timing

EE141 Timing Issues 3 Latch Parameters D Clk Q D Q t c-q t hold PW m t su t d-q Delays can be different for rising and falling data transitions T

EE141 Timing Issues 4 Register Parameters D Clk Q D Q t c-q t hold T t su Delays can be different for rising and falling data transitions

EE141 Timing Issues 5 Clock Uncertainties Sources of clock uncertainty

EE141 Timing Issues 6 Clock Nonidealities  Clock skew  Spatial variation in temporally equivalent clock edges; deterministic + random, t SK  Clock jitter  Temporal variations in consecutive edges of the clock signal; modulation + random noise  Cycle-to-cycle (short-term) t JS  Long term t JL  Variation of the pulse width  Important for level sensitive clocking

EE141 Timing Issues 7 Clock Skew and Jitter  Both skew and jitter affect the effective cycle time  Only skew affects the race margin Clk t SK t JS

EE141 Timing Issues 8 Clock Skew # of registers Clk delay Insertion delay Max Clk skew Earliest occurrence of Clk edge Nominal –  /2 Latest occurrence of Clk edge Nominal +  /2 

EE141 Timing Issues 9 Positive and Negative Skew

EE141 Timing Issues 10 Positive Skew Launching edge arrives before the receiving edge

EE141 Timing Issues 11 Negative Skew Receiving edge arrives before the launching edge

EE141 Timing Issues 12 Timing Constraints Minimum cycle time: T -  = t c-q + t su + t logic Worst case is when receiving edge arrives early (positive  )

EE141 Timing Issues 13 Timing Constraints Hold time constraint: t (c-q, cd) + t (logic, cd) > t hold +  Worst case is when receiving edge arrives late Race between data and clock

EE141 Timing Issues 14 Impact of Jitter

EE141 Timing Issues 15 Longest Logic Path in Edge-Triggered Systems Clk T T SU T Clk-Q T LM Latest point of launching Earliest arrival of next cycle T JI + 

EE141 Timing Issues 16 Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early, the data will not be too late if: Minimum cycle time is determined by the maximum delays through the logic T c-q + T LM + T SU < T – T JI,1 – T JI,2 -  T c-q + T LM + T SU +  + 2 T JI < T Skew can be either positive or negative

EE141 Timing Issues 17 Shortest Path Clk T Clk-Q T Lm Earliest point of launching Data must not arrive before this time Clk THTH Nominal clock edge

EE141 Timing Issues 18 Clock Constraints in Edge-Triggered Systems Minimum logic delay If launching edge is early and receiving edge is late: T c-q + T LM – T JI,1 < T H + T JI,2 +  T c-q + T LM < T H + 2T JI + 

EE141 Timing Issues 19 How to counter Clock Skew?

EE141 Timing Issues 20 Flip-Flop – Based Timing Flip -flop Logic    Flip-flop delay Skew Logic delay T SU T Clk-Q Representation after M. Horowitz, VLSI Circuits 1996.

EE141 Timing Issues 21 Flip-Flops and Dynamic Logic   Logic delay T SU T Clk-Q   Logic delay T SU T Clk-Q Precharge Evaluate Precharge Flip-flops are used only with static logic

EE141 Timing Issues 22 Latch timing D Clk Q t D-Q t Clk-Q When data arrives to transparent latch When data arrives to closed latch Data has to be ‘re-launched’ Latch is a ‘soft’ barrier

EE141 Timing Issues 23 Single-Phase Clock with Latches Latch Logic  Clk P PW T skl T skt

EE141 Timing Issues 24 Latch-Based Design L1 Latch Logic L2 Latch  L1 latch is transparent when  = 0 L2 latch is transparent when  = 1

EE141 Timing Issues 25 Slack-borrowing

EE141 Timing Issues 26 Latch-Based Timing L1 Latch Logic L2 Latch    L1 latch L2 latch Skew Can tolerate skew! Long path Short path Static logic

EE141 Timing Issues 27 Clock Distribution Clock is distributed in a tree-like fashion H-tree

EE141 Timing Issues 28 More realistic H-tree [Restle98]

EE141 Timing Issues 29 The Grid System No rc-matching Large power

EE141 Timing Issues 30 Example: DEC Alpha 21164

EE141 Timing Issues Clocking  2 phase single wire clock, distributed globally  2 distributed driver channels  Reduced RC delay/skew  Improved thermal distribution  3.75nF clock load  58 cm final driver width  Local inverters for latching  Conditional clocks in caches to reduce power  More complex race checking  Device variation t rise = 0.35ns t skew = 150ps t cycle = 3.3ns Clock waveform Location of clock driver on die pre-driver final drivers

EE141 Timing Issues 32

EE141 Timing Issues 33 Clock Skew in Alpha Processor

EE141 Timing Issues 34  2 Phase, with multiple conditional buffered clocks  2.8 nF clock load  40 cm final driver width  Local clocks can be gated “off” to save power  Reduced load/skew  Reduced thermal issues  Multiple clocks complicate race checking t rise = 0.35nst skew = 50ps t cycle = 1.67ns EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS Global clock waveform

EE141 Timing Issues Clocking

EE141 Timing Issues 36 EV6 Clock Results GCLK Skew (at Vdd/2 Crossings) ps ps GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%)

EE141 Timing Issues 37 EV7 Clock Hierarchy + widely dispersed drivers + DLLs compensate static and low- frequency variation + divides design and verification effort - DLL design and verification is added work + tailored clocks Active Skew Management and Multiple Clock Domains

EE141 Timing Issues 38 Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 2) Ordering of events is implicit in logic 1) Completion is ensured by careful timing analysis Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol

EE141 Timing Issues 39 Synchronous Pipelined Datapath

EE141 Timing Issues 40 Self-Timed Pipelined Datapath Check Textbook for details!