Process integration

Wafer selection active role for the wafer ? passive role ? –thermal conductivity –optical transparency –flat, smooth mechanical support compatibility with equipment ? thermal limitations ? contamination ? Especially glass in Si fabs !

Metal heater processing 1.Metal sputtering (or evaporation) 2.Photoresist spinning & baking 3.Lithography with resistor mask 4. Resist image development 5. Metal etching 6. Photoresist stripping Can be done on any wafer ! Glass wafers, polymer,...

Diffused heater processing 1.Thermal oxidation 2.Photoresist spinning & baking 3.Lithography with heater mask 4.Oxide etching 5.Photoresist stripping 6.Wafer cleaning 7.Diffusion (in furnace) 8.Oxide etching 9.New thermal oxidation ! Only applicable on silicon wafers !

Diffused vs. metal resistor Size determined by: Lithography + diffusion Always isotropic !! 2 µm linewidth + 1 µm diffusion depth  4 µm wide resistor Size determined by: -lithography+ etching Can be anisotropic. 2 µm linewidth  2 µm wide resistor

Example:solar cell process flow top metallization anti-reflective coating (ARC) Backside metallization p-substrate p+ diffusion n -diffusion The contact holes in anti-reflective coating are non-critical The metallization alignment to contact holes is critical (in case of misalignment, metal does not fully cover holes, and gases, liquids, dirt can penetrate into silicon)

Front end processing wafer selection (p-type) wafer cleaning thermal oxidation photoresist spinning on front backside oxide etching resist stripping wafer cleaning p+ backside diffusion (10 19 cm -3 ) front side oxide etching wafer cleaning n-diffusion (10 17 cm -3 ) FRONT END = STEPS BEFORE METALLIZATION backside metallization top metallization antireflection coating (ARC) p-substrate p+ diffusion n -diffusion

Backend processing resist spinning on front metal sputtering on back side resist stripping wafer cleaning PECVD nitride deposition lithography for contact holes etching of nitride resist stripping wafer cleaning metal deposition on front side lithography for front metal metal etching photoresist stripping contact improvement anneal backside metallization top metallization antireflection coating (ARC) p-substrate p+ diffusion n -diffusion BACKEND IS PROCESS AFTER FIRST METAL DEPOSITION

Materials stability at high temperatures high temperature (>900°C; diffusion fast) really only Si, SiO 2, Si 3 N 4, SiC intermediate temperature ( °C) refractory metals not in contact with Si metal compatible temperature (<450 °C) Si/metal interface stable, glass wafers polymer compatible (<120 °C) evaporation, sputtering (lift-off resist)

Thermal budget Time-temperature limits that the device can endure. High temperature causes: -diffusion (in all atmospheres) -oxidation (in oxidative atmosphere) -damage recovery Some of these are wanted effects, some are problems: -implantation damage removed -dopants driven deeper -silicon oxidation competes with diffusion

Thin film annealing effects: physical grain growth (in polycrystalline materials) crystallization (in amorphous materials) diffusion of dopants (e.g. boron in silicon) melting (e.g. aluminum melting point 653 o C, very low) thermal expansion and thermal stresses desorption of adsorbed specie

Thin film annealing effects: chemical Oxidation of surface: Ti + O 2  TiO 2 reactions between thin films (Al 12 W) reactions between substrate and thin film (TiSi 2 ) dissolution (e.g. silicon dissolves into aluminum) corrosion (Cl residues: AlCl 3 )

Active vs. passive cleaning Cleanroom (and its subsystems) provide passive cleanliness Wafer cleaning provides active cleaning

Wafer cleaning removal of added contamination ultrapure chemicals (very expensive) particle-free (filtered 0.3 µm) always includes rinsing & drying steps (with ultrapure water and nitrogen)

Surface preparation leaves wafer in known surface condition eliminates previous step peculiarities eliminates waiting time effects Wafer cleaning is the same as surface preparation; it is just a different viewpoint of wafer cleanliness

Contact angle θ Ultrahydrophilic (θ ~ 10 o )Hydrophilic (θ ~ 70 o ) Hydrophobic (θ >90 o ) If surface is hydrophobic, water-based cleaning chemicals will be ineffective.

Equipment: 1- or 2-sided processing Beam processes 1-sidedImmersion processes 2-sided -photon beams (=lithography)-liquids (=wet etching) -atom beams (=evaporation)-liquids (=cleaning) -ion beams (=implantation)-gases (= oxidation, diffusion) -mixture of these (=plasmas)-gases (=CVD)

Both side processes Thermal oxidation CVD Wet etching Wet cleaning

Single side processes PECVD, RIE Ion implantation

Wet etch vs. plasma etch Oxide wet etch in HF Oxide plasma etch in CHF 3 Film remains on backside Vertical sidewalls profile Film removed from backside Undercutting etch profile

Fluidic filters a b c d

Fluidic filters (2) Criteria: Need one or two wafers ? Cost, bonding... Pass size determined by litho ? Bonding ? Flow resistance ? Aperture ratio. Clogging ? Active cleaning ?

Alignment and design rules Example of Overlap rule: Coinciding structures must overlap by (LW/3)

Alignment and design rules Example of Overlap rule: Coinciding structures must overlap by (LW/3)

Design rules (2) a b Overlap rule eliminates alignment errors and mask size errors.

Design rules (3) Minimum linewidth rule Minimum spacing rule Overlap rules for structures on different layers Breaking design rules ruins your process (=you are expecting too much from the process) Within one layer

Self-alignment: CMOS gate

Self-alignment: sawtooth grid

NbN bolometer in SEM Figure courtesy Leif Grönberg, VTT

Bolometer mask view 1) Oxidation 2) Metal deposition 3) Lithography 4) Metal etching 5) Resist strip Bolometer process flow 6) 2 nd lithography 7) Oxide etch 8) Silicon isotropic etch

Critical vs. non-critical steps Al Bonding defines 1 µm capacitor gapBonding creates 500 µm channel

Order of process steps

Process monitoring Measurement = general term Monitoring = quick measurement in production ProblemMeasurementMonitoring Gate oxide thicknessTEM cross-sectionEllipsometer Implant doseSIMS profileSheet resistance StressX-ray rocking curveWafer bow Ti:N ratio in TiNAuger spectroscopyResistivity

Mapping and uniformity In order to check something across the wafer, we must have a quick monitoring measurement that can be repeated many times. Ellipsometer measurement of dry oxide thickness

Cost of measurement If the wafer is consumed in the measurement, the cost of measurement will be at least the wafer cost  tens of euros € equipment, operator cost is € for 5 years, 1 sec/measurement, 49 points/wafer  1500 wafers/day, 2.5 million/5 years  cost of mapping the wafer is 8 cents. If chips/wafer  4 µcents/chip Hot-wall MOCVD for highly efficient and uniform growth of AlN A. Kakanakova-Georgieva · R. R. Ciechonski · U. Forsberg · A. Lundskog · E. Janzén Crystal Growth & Design 2008