7th PXD/SVD Workshop, Prague, January 2015 Rainer Richter, MPG Halbleiterlabor 1 Pilot Run - Status and Plans PXD9-6 Rainer Richter for the MPG Halbleiterlabor.

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Presentation transcript:

7th PXD/SVD Workshop, Prague, January 2015 Rainer Richter, MPG Halbleiterlabor 1 Pilot Run - Status and Plans PXD9-6 Rainer Richter for the MPG Halbleiterlabor

7th PXD/SVD Workshop, Prague, January 2015Rainer Richter, MPG Halbleiterlabor 2 Pilot run wafers Batc h WTypeContacts Testing status I24dummyto poly, poxn, noxnongoing I25dummyto poly, poxn, noxnongoing I26dummyto poly, poxn, noxnongoing I27dummyto poly, poxn, noxnongoing II23dummyallfrom II30hotallfrom II35hotallfrom II36hotallfrom

7th PXD/SVD Workshop, Prague, January 2015 Rainer Richter, MPG Halbleiterlabor 3 - first metal (al1n) Al deposition, lithography, etching done first electrical measurements (talks by Paola and me) - metal1 metal2 vias (co2n) lithography and etchingdone - second metal (al2n) Al deposition (all wafers)done lithography and etching (dummies) done lithography and etching (project wafers)done (still in inspection) -Break for intense measurements can start next week PXD9-6 production status

Module label 7th PXD/SVD Workshop, Prague, January 2015 Rainer Richter, MPG Halbleiterlabor 4 Containing: Wafer number and module type -> unique labels 150µm height -> magnifying glass

7th PXD/SVD Workshop, Prague, January 2015 Rainer Richter, MPG Halbleiterlabor 5 PXD9-6 production (pilot run) is running smoothly and in time 1 week ahead of schedule first electrical measurements (after metal 1) look promising (see next talks) Now: metal 2 is finished Top side of the DEPFET matrix is ‚ready‘ (does not need copper) Intense measurements are planned in the next 2-3 weeks Summary

PXD9 Pilot production (iii) 7th PXD/SVD Workshop, Prague, January 2015 Rainer Richter, MPG Halbleiterlabor 6 Cons - Risk to loose of 2 or 3 (2nd grade) PXD9 wafers if we finally find still a severe bug on EMCM modules - No time to wait with the remaining wafer on the results of fully equipped and tested modules But we could wait with the first batch for the intermediate tests of metal1/metal2 And we could stop before Copper in order to be able to react in the third metal layer on unforeseen results (e.g. Gated Mode)