Multiplier: Functions Discussion D7.2 Example 19.

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Presentation transcript:

Multiplier: Functions Discussion D7.2 Example 19

Multiplier Binary Multiplication A VHDL Multiplier The Multiplication Operator A Multiplication Function

Binary Multiplication

13 x C = 156

Hex Multiplication

61 x D x 5A 262 A x D = 82, A x 3 = 1E + 8 = x D = 41, 5 x 3 = F + 4 = = Dec Hex

Multiplication 13 x = 8Fh 1101 x

Multiplier Binary Multiplication A VHDL Multiplier The Multiplication Operator A Multiplication Function

1101 x

-- Example 19a: 4-bit multiplier library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity mult4a is port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); p : out STD_LOGIC_VECTOR(7 downto 0) ); end mult4a; architecture mult4a of mult4a is begin process(a,b) variable pv,bp: STD_LOGIC_VECTOR(7 downto 0); begin pv := " "; bp := "0000" & b; for i in 0 to 3 loop if a(i) = '1' then pv := pv + bp; end if; bp := bp(6 downto 0) & '0'; end loop; p <= pv; end process;

Multiplier Simulation

Multiplier Binary Multiplication A VHDL Multiplier The Multiplication Operator A Multiplication Function

-- Example 19a: 4-bit multiplier library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity mult4b is port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); p : out STD_LOGIC_VECTOR(7 downto 0) ); end mult4b; architecture mult4b of mult4b is begin p <= a * b; end mult4b;

Multiplier Binary Multiplication A VHDL Multiplier The Multiplication Operator A Multiplication Function

-- Example 19c: 4-bit multiplier function library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity mult4c is port( sw : in STD_LOGIC_VECTOR(7 downto 0); ld : out STD_LOGIC_VECTOR(7 downto 0) ); end mult4c;

architecture mult4c of mult4c is function mul(a,b : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is variable pv,bp: STD_LOGIC_VECTOR(7 downto 0); begin pv := " "; bp := "0000" & b; for i in 0 to 3 loop if a(i) = '1' then pv := pv + bp; end if; bp := bp(6 downto 0) & '0'; end loop; return pv; end function;

signal a1: STD_LOGIC_VECTOR(3 downto 0); begin a1 <= sw(7 downto 4); ld <= mul(a1,sw(3 downto 0)); end mult4c;

Multiplier Binary Multiplication A VHDL Multiplier The Multiplication Operator (revisited) A Multiplication Function

library IEEE;use IEEE.std_logic_1164.all; package std_logic_arith is type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; subtype SMALL_INT is INTEGER range 0 to 1; function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; function "*"(L: SIGNED; R: SIGNED) return SIGNED; function "*"(L: SIGNED; R: UNSIGNED) return SIGNED; function "*"(L: UNSIGNED; R: SIGNED) return SIGNED; function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR; function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR; std_logic_arith.vhd

function mult(A,B: UNSIGNED) return UNSIGNED is constant msb: integer:=A'length+B'length-1; variable BA: UNSIGNED(msb downto 0); variable PA: UNSIGNED(msb downto 0); begin if (A(A'left) = 'X' or B(B'left) = 'X') then PA := (others => 'X'); return(PA); end if; PA := (others => '0'); BA := CONV_UNSIGNED(B,(A'length+B'length)); for i in 0 to A'length-1 loop if A(i) = '1' then PA := PA+BA; end if; for j in msb downto 1 loop BA(j):=BA(j-1); end loop; BA(0) := '0'; end loop; return(PA); end; 1101 x

function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is begin return mult(CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)); end;

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; std_logic_unsigned.vhd package STD_LOGIC_UNSIGNED is function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;

function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is constant length: INTEGER := maximum(L'length, R'length); variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0); begin result := UNSIGNED(L) * UNSIGNED(R); return std_logic_vector(result); end; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package body STD_LOGIC_UNSIGNED is std_logic_unsigned.vhd (cont.)