© 2006 Xilinx, Inc. All Rights Reserved System On Chip DAPNIA Day, November 10th Presenter : Olivier REGNAULT / SILICA FAE Xilinx

CEA Saclay, Dapnia day System On Chip solution SOC Introduction Challenge : – Create High speed frequency design – Use very High speed communication links – Keep flexibility for modification Xilinx response : – FPGA provides hardware structure that enables integrated high speed design (up to 550Mhz) – FPGA offers integrated differential solution (LVDS) for DDR high speed communication + Hard IP Transceiver (Up to 3.2Gbps) – FPGA is by default the best hardware flexible solution offered through hardware reconfiguration (even partial reconfiguration) – FPGA can implement processor core as Soft IP core (Microblaze) Hard IP core (PowerPC)

CEA Saclay, Dapnia day System On Chip solution Create High speed frequency design This is the first thing we expect from an FPGA. What we know : – FPGA can reproduce Chip set such as DSP – FPGA enables parallel structure – FPGA integrates features to improve performance and decrease the logic needs

CEA Saclay, Dapnia day System On Chip solution Number of Taps MAC Engine FIR Filter Samples 31 × 12 Coefficients 16 × 11 Sample in Sample Address Coefficient Address D Q CE + + D Q Max Sample Rate = Clock Rate MHz = 31 = 17.7 MHz × Several clock cycles between samples The clock rate must be higher than the sample rate Load

CEA Saclay, Dapnia day System On Chip solution For the very highest sample rates, the full parallel structure performs all calculations in parallel, and registers provide the ultimate in “memory” bandwidth Max Sample Rate = Clock Rate = 400 MHz (Virtex5™ FPGA) Sample rate is essentially independent of number of taps. Size is set by the number of taps Adder Tree Sample Latency Registers: One per tap Sample in Sample out Full Parallel FIR Filter

CEA Saclay, Dapnia day System On Chip solution Systolic FIR Filter Coefficients are from left to right, which causes the latency to be as large and grow with the increase of coefficients Input time delay series is created inside the DSP48 slice for maximum performance irrespective of the number of coefficients without additional cost Max Sample Rate = Clock Rate= 550 MHz This filter structure, while referred to as a systolic FIR filter, is really a Direct Form with one extra stage of pipelining K0K1 K29K30 0 DSP48 Slice opmode = DSP48 Slice opmode = Sample in Sample out

CEA Saclay, Dapnia day System On Chip solution Components interconnection: – Data width may be large and may require a huge number of IOBs PCB Integrity signal  Xilinx Sparse Chevron + LVDS Power consumption  LVDS System communication – Ethernet  Xilinx includes Tri-mode MAC Hard IP (10/1000/1000Mbps) in Virtex4 FX and Virtex5 LXT – PCI Express  Xilinx includes PCI Express Hard IP in the newest Virtex5 LXT family. – PCIe x1,x2,x4 and x8 … Use very high Speed communication links

CEA Saclay, Dapnia day System On Chip solution High-Speed Serial Applications Each Application has Unique Requirements Backplane Interface Toughest channel to drive Backplane Interface Toughest channel to drive Optics Interface SFP Modules - GE, OC-48 XFP Modules - 10GE, OC-192 Optics Interface SFP Modules - GE, OC-48 XFP Modules - 10GE, OC-192 Board-to-Board Cables, short reach optics Board-to-Board Cables, short reach optics Chip-to-Chip - Aurora Chip-to-Chip - Aurora

CEA Saclay, Dapnia day System On Chip solution Advantages of Serial Connectivity Single Ended I/O Data In Clk In Data Out Clk Out Noise Limited above ~200 Mbps (Single Data Rate) Serial I/O +-+- X Clk Data +-+- CDR Clk Data Eliminates traditional noise and clock-skew issues Gbps and up! Differential I/O (e.g., LVDS) Data In Clk In Data Out Clk Out Clock skew Limited above ~1.0 Gbps (Double Data Rate) Traditional I/O schemes have limited bandwidth Transceiver

CEA Saclay, Dapnia day System On Chip solution Transceiver Block Diagram TX+ TX- RX+ RX- TXDATA RXDATA Channel Bonding and Clock Correction TX Clock Generator RX Clock Recovery REFCLK Deserializer Comma Det. Serializer Receive Buffer Transmit Buffer Transmitter Receiver Transceiver Module *32/16/8 bits 50 – MHz FIFOFIFO 8B / 10B Encode 8B / 10B Decode Elastic Buffer **20X Multiplier Loop-back Physical Coding Sublayer Physical Media Attachment Mindspeed IP CRCCRC CRC TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 FPGAFABRICFPGAFABRIC PCBOARDPCBOARD

CEA Saclay, Dapnia day System On Chip solution Tx Rx DiscretePHYDiscretePHY Tx Rx Benefits of PCIe Hard Block Saves logic resources – 5,000 to 10,000 LUTs Saves system cost Saves power Saves design time – Automated design flow Guaranteed functionality and performance Hard core with GTP Transceivers Soft core

CEA Saclay, Dapnia day System On Chip solution Keep Flexibility: Processor embedded in an FPGA Processor embedded in an FPGA consists of the following – FPGA hardware design – Software design Software routines Interrupt service routines (optional) Real Time Operating System (RTOS) (optional)

CEA Saclay, Dapnia day System On Chip solution MicroBlaze Processor-Based Embedded Design (Soft IP) Flexible Soft IP MicroBlaze  32-Bit RISC Core UART 10/100 E-Net Memory Controller Off-Chip Memory FLASH/SRAM Fast Simplex Link 0,1….7 Custom Functions Custom Functions BRAM Local Memory Bus D-Cache BRAM I-Cache BRAM Configurable Sizes Possible in Virtex-II Pro Arbiter OPB On-Chip Peripheral Bus CacheLink SRAM

CEA Saclay, Dapnia day System On Chip solution PowerPC Processor-Based Embedded Design (Hard IP) PowerPC 405 Core Dedicated Hard IP Flexible Soft IP RocketIO™ Full system customization to meet performance, functionality, and cost goals DCR Bus UART GPIO On-Chip Peripheral Hi-Speed Peripheral GB E-Net e.g. Memory Controller Arbiter On-Chip Peripheral Bus OPB Arbiter Processor Local Bus InstructionData PLB DSOCM BRAM ISOCM BRAM Off-Chip Memory ZBT SSRAM DDR SDRAM SDRAM Bus Bridge IBM CoreConnect on-chip bus standard PLB, OPB, and DCR

CEA Saclay, Dapnia day System On Chip solution APU Interface Virtex™-4 FX devices Coprocessor interface – Connects the PowerPC™ processor to fabric – Offload computations to fabric; for example, hardware FPU Extends native PowerPC 405 processor instruction set Decodes but does not execute instructions Tighter integration between processor and fabric I-Side PLB D-Side PLB Control Logic BRAM BRAM 405Core DSOCMController ISOCMController APU Controller

CEA Saclay, Dapnia day System On Chip solution Embedded Development Kit What is the Embedded Development Kit (EDK)? – The Embedded Development Kit is the Xilinx software suite for designing complete embedded programmable systems – The kit includes all the tools, documentation, and IP that you require for designing systems with embedded IBM PowerPC™ hard processor cores, and/or Xilinx MicroBlaze™ soft processor cores – It enables the integration of both hardware and software components of an embedded system

CEA Saclay, Dapnia day System On Chip solution Embedded System Tools GNU software development tools – C/C++ compiler for the MicroBlaze™ and PowerPC™ processors (gcc) – Debugger for the MicroBlaze and PowerPC processors (gdb) Hardware and software development tools – Base System Builder Wizard – Hardware netlist generation tool: PlatGen – Software library generation tool: LibGen – Simulation model generation tool: SimGen – Create and Import Peripheral wizard – Xilinx Microprocessor Debugger (XMD) – Hardware debugging using ChipScope™ Pro Analyzer cores – Eclipse IDE-based Software Development Kit (SDK) – Application code profiling tools – Virtual platform generator: VPGen – Flash Writer utility

CEA Saclay, Dapnia day System On Chip solution Detailed EDK Design Flow Processor IP MPD Files system.ucf Create FPGA Programming (system.bit) MHS File system.mhs PlatGen FPGA Implementation (ISE/Xflow) Hardware Data2MEM download.bit Compile Link Object Files Executable Libraries Source Code (C code) LibGen MSS File system.mss EDIF IP Netlists Source Code (VHDL/Verilog) Synthesis Standard Embedded Software Flow Standard Embedded Hardware Flow

CEA Saclay, Dapnia day System On Chip solution Xilinx Solutions

CEA Saclay, Dapnia day System On Chip solution Virtex-5 FPGA Family The Ultimate System Integration Platform Logic On-chip RAM DSP Capabilities Serial I/Os Parallel I/Os PowerPC Logic * Normalized to highest quantity Now Logic/Serial DSP/Serial Very soon Embedded/Serial 2007 Built on the Success of ASMBL Platform Roadmap

CEA Saclay, Dapnia day System On Chip solution Virtex-5 LX Platform X X = IO capacity

CEA Saclay, Dapnia day System On Chip solution Virtex-5 LXT FPGAs Industry’s First 65nm Serial I/O Solution * Comparisons made to 90nm Virtex-4 FPGA devices Built on Virtex-5 LX platform 65nm ExpressFabric technology FPGA industry’s first built-in PCIe & Ethernet blocks Compliance tested at PCISIG Plugfest and UNH IOL Industry’s lowest power 65nm transceivers: 3.2Gbps Support for all major protocols: PCIe, GbE, XAUI, OC-48, etc. Six devices ranging from 30K to 330K logic cells 5VLX30T, 5VLX50T and 5VLX110T Available Now! Available Now!

CEA Saclay, Dapnia day System On Chip solution Virtex-5 LXT Platform 5VLX30T5VLX50T5VLX85T5VLX110T5VLX220T5VLX330T Logic Cells 30,72046,08082,944110,592221,184331,776 LUT6/Flip-Flops 19,20028,80051,84069,120138,240207,360 Total Distributed RAM (Kbits) ,1202,2803,420 Total Block RAM (Kbits) 1,2962,1603,8885,3287,63211,664 Clock Management Tiles (CMT) DSP48E Slices RocketIO GTP Channels PCIe Subsystem Blocks /100/1000 EMACs EasyPath No Yes PackageSize FF ,8 FF ,12 640,16 FF ,16 960,24 X,Y X = SelectIO, Y=RocketIO Channels

CEA Saclay, Dapnia day System On Chip solution Conclusion Depending of your Digital system, you may use Xilinx FPGA as the solution for System On Chip. – Today Xilinx can provide in 1 component (Virtex4 or Virtex5): Embedded PowerPC 405 Embedded Ethernet MAC 10/100/1000 Embedded MAC DSP Embedded High Speed Transceivers Embedded PCI Express (Virtex5 only) Programmable Logic Cells ….