Arnold Ginetti, Taranjit Kukal, Steve Durrill, Balvinder Singh, Madhur Sharma April 2016 Cross/Multi Fabric Design Environment Virtuoso  Allegro

2© 2015 Cadence Design Systems, Inc. All rights reserved. Customer Goals & Challenges –IC simulations become more meaningful in context of Package (PKG) & Board (PCB) –Analog IC designs require PKG/PCB components to fully load the circuit –Package & PCB Parasitic effects are critical to Analog/RF IC designs –IC, PKG, & PCB designed by different teams using different design tools, & physically located in different geographies PKG/PCB aware IC simulations in Virtuoso –PKG could be designed in Virtuoso schematic –There could be cases where there is no schematic for the PKG –PCB schematic for the board may or may not be available –Models extracted could be cross-fabric, region-based / pin-based –Complete PCB and/or PKG extraction, resulting in single large S-Parameter model is common for simple designs. –  need to build a cross-fabric schematic representing the extracted PCB/PKG/IC Introduction

3© 2015 Cadence Design Systems, Inc. All rights reserved. CFDE Automatic cross-fabric schematic creation Allegro schematic layout Models RC/S-params Sigrity CFDE Schematic

4© 2015 Cadence Design Systems, Inc. All rights reserved. CFDE Schematic descend Descend Allegro schematic (view only) Descend VSE test-bench schematic

5© 2015 Cadence Design Systems, Inc. All rights reserved. CFDE Schematic to schematic cross-probe Pin-based model Net-based model Instance Cross probe with DEHDL to see components and ( comprehend design) in master schematic Special visualization of components in DEHDL forming parasitic extraction group Split symbol DEHDL symbols cross-probe with flat VSE symbol

6© 2015 Cadence Design Systems, Inc. All rights reserved. CFDE Schematic to layout cross-probe

7© 2015 Cadence Design Systems, Inc. All rights reserved. CFDE roadmap and status Phase1: Q2Phase3: Q1 2016Phase2: Q3 Complete PCB/PKG connectivity. Mono-fabric Sigrity extraction. Creation of Virtuoso Schematic from PCB/PKG layout Model import into VSE from Sigrity Connectivity visualization Netlist and simulation DEHDL2VSE translation PCB/PKG specification from Allegro layout PCB/PKG specification from Allegro schematic. Place as in PCB/PKG Layout Cross Probe and Highlight with PCB/PKG layout Customer feedback Place as in PCB/PKG Schematic Cross Probe and Highlight with DEHDL Auto-wire Handling vector-symbols DEHDL look & feel like VSE Customer feedback

8© 2015 Cadence Design Systems, Inc. All rights reserved. CFDE roadmap and status Phase4: Q onwards Virtuoso-SiP flow integrated into CFDE Cross-fabric Sigrity extraction Interface to third party applications. Mapping Model ports to schematic interfaces to allow import of 3 rd party solver models Ability to merge geometries across IC/PKG/PCB and combined geometry extraction Cross highlight ports of cross-fabric model in VSE to respective fabrics Schematic driven Sigrity solvers Include Virtuoso-SiP (ftb and die-codesign) as part of CFDE

9© 2015 Cadence Design Systems, Inc. All rights reserved. Board Layout connectivity Generation of Board File From Allegro Layout

10© 2015 Cadence Design Systems, Inc. All rights reserved. Generation of Model File(s) From PowerSI Extracted Parasitic Models Board Layout Connectivity

11© 2015 Cadence Design Systems, Inc. All rights reserved. Create PCB Layout Model… Extracted Parasitic Models Board Layout Connectivity Automatic Virtuoso schematic creation

12© 2015 Cadence Design Systems, Inc. All rights reserved. Create PCB Layout Model… board.pcb Target Text View Name boardModel Target Board View Name physical 5x Cellview Generation Specification Extracted Parasitic Models Board Layout Connectivity Automatic Virtuoso schematic creation

13© 2015 Cadence Design Systems, Inc. All rights reserved. Create PCB Layout Model… board.pcb Target Text View Name boardModel Target Board View Name physical Automatic Virtuoso schematic creation

14© 2015 Cadence Design Systems, Inc. All rights reserved. IC Symbols Board Discretes Parasitic Model Automatic Virtuoso schematic creation

15© 2015 Cadence Design Systems, Inc. All rights reserved. Automatic Virtuoso schematic creation Connection by name

16© 2015 Cadence Design Systems, Inc. All rights reserved. Automatic Virtuoso schematic creation Connection visualization

17© 2015 Cadence Design Systems, Inc. All rights reserved. ADE-XL Simulation

18© 2015 Cadence Design Systems, Inc. All rights reserved. LVS Board Layout Connectivity Virtuoso Schematic LVS reporting

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Allegro, PowerSI, Spectre, Virtuoso, and the Cadence logo are registered trademarks and Sigrity is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.