DESIGN OF A DYNAMICALLY RECONFIGURABLE PIPELINED RISC PROCESSOR 1 st Review 19 th March 2015 Azmath Moosa Dept. of Electronics Engg. School of Engg. & Tech, Pondicherry University Md. Aneesh Dept. of Electronics Engg. School of Engg. & Tech, Pondicherry University Under the guidance of

Proposed Design - ISA Micro-Op AddressOperands

Fluid Core ISA v Micro-Op Address Branch Condition or Destination Register Reg AReg B Reg AImmediate Immediate RRR RRI RI

The Pipeline FetchDecodeExecute Memory Access Write Back MicroStore TypeMod. SelOperation Register File Operand AOperand B Dest. Reg/BC

The Pipeline FetchDecodeExecute Memory Access Write Back ALUShifter Custom Module TypeMod. SelOperationOperand AOperand B Dest. Reg/BC Result/AddressStore Operand Dest. Reg/BC Type

The Pipeline FetchDecodeExecute Memory Access Write Back Result/AddressStore Operand Dest. Reg/BC Type Data Memory (External) Branch Unit ResultTypeDest. Reg/BC

The Pipeline FetchDecodeExecute Memory Access Write Back ResultTypeDest. Reg/BC Register File

Comparison CategoryNIOS 2MicroBlazeOpenRISC Fluid Core Fluid Core v2 Datapath Width Fixed 32 bit 32 or 64 8, 16, 32, 64… 8, 16, 32, 64 Floating Point Unit IEEE 754 No, as peripheral No, can be added No, Can be added Pipeline 6 stages3 stages5 stagesNone5 stages Custom Instructions Upto 256NoneUnlimited Register File Size 32 Unlimited Max Clock Frequency 200 MHz 300 MHz (ASIC)56 MHz 216 Mhz Area 1800 LUTs 1269 LUTsNA800 LUTs 700 LUTs

Scalability - Area

Scalability - Speed

Future Work Hazard Management Technique – Operand Forwarding Implement write to Micro-Op store instructions Assembler Configuration FPGA Implementation

References Pocek, Kenneth, Russell Tessier, and André DeHon. "Birth and adolescence of reconfigurable computing: A survey of the first 20 years of field-programmable custom computing machines." Highlights of the First Twenty Years of the IEEE International Symposium on Field-Programmable Custom Computing Machines J. Tong,, "Soft-Core Processors for Embedded Systems," IEEE Conferences on Reconfigurable Computing, Vol., no., pp Chapman, Ken, PicoBlaze 8-Bit Microcontroller for Virtex-E and Spartan-II/IIE Devices, Xilinx, version 2.1 Michael Gschwind, Valentina Salapura,, FPGA Prototyping of a RISC Processor Core for Embedded Applications, IEEE Transactions on VLSI, vol 9, no 2, p J. Gray, “Designing a Simple FPGA-Optimized RISC CPU and System-on-a-Chip”, DesignCon’2001, online at

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