Presented by Rania Kilany

 Energy consumption  Energy consumption is a major concern in many embedded computing systems.  Cache Memories 50%  Cache Memories consumes 50% of the total energy.  Desktop systems  Desktop systems runs a very wide range of applications and the cache architecture is set to work well with the given applications, technology and cost.  Embedded systems  Embedded systems are designed to run a small range of well- defined applications. So the cache architecture can have both increased performance as well as lower energy consumption.

Power dissipation in CMOS circuits: 1. Static power 1. Static power dissipation due to leakage current 2. Dynamic power 2. Dynamic power dissipation due to logic switching current and the charging and discharging of the load capacitance. 3. Energy consumption 3. Energy consumption :  Fetching instruction and data from off-chip memory because of the high off-chip capacitance and large off-chip memory storage.  The Microprocessor stalls while waiting for the instruction and/or data.

The total energy due to memory accesses is as follows: Energy_mem = Energy_dynamic + Energy_static ….(1) Energy_dynamic = cache_hits * energy_hit + cache_misses * energy_miss Energy_miss = energy_offchip_access + energy_uP_stall + energy_cache_block_fill Energy_static = Energy_static = cycles * energy_static_per_cycle

Cache size = 8 Kbytes Block size = 32 bytes 32-bit address four-way set-associative

A Direct Mapped Cache Less power per access Four-way set associative cache More power per access one tag and one data array are read Four tags and Four data arrays are read Low Miss Rate

A Direct Mapped Cache Four-way set associative cache one tag and one data array are read Four tags and Four data arrays are read High Miss Rate Higher energy due to longer time & High power for accessing the next level memory Lowers Cache Miss Rate Reduce Time and Power that would have been caused by misses

Tuning the associativity to a particular application is extremely important to minimize energy Motivating the need for a cache with configurable associativity

reconfigured way-concatenation.  The cache can be reconfigured by software to be direct- mapped, two-way, or four-way set associative, using a technique called way-concatenation.  reconfigured Cache  reconfigured Cache have very little size and performance overhead.  Way-concatenation  Way-concatenation reduces energy caused by dynamic power.  Way-shutdown  Way-shutdown reduces energy caused by static power if combined with way-concatenation.

 Develop a cache architecture whose associativity could be configured as one, two or four ways, while still utilizing the full capacity of the cache.  6 index four-way  6 index bits for a four-way cache  7 index two-way  7 index bits for a two-way cache  8 index one-way  8 index bits for a one-way cache. 8 or more  Could be extended for 8 or more ways.

How much the configurability of such a cache increases access time compared to a conventional four-way cache??  the configuration circuit is not on the cache access critical path, the circuit executes concurrently with the index decoding. speed  Set the sizes of the transistors in the configure circuit such that the speed of the configure circuit is faster than that of the decoder. area  The configure circuit area is negligible.

 Change two inverters on the critical path into NAND gates: one inverter after the decoder, and one after the comparator. delay  Increasing the sizes of the NAND gates to three times their original size to reduce the critical path delay to the original time. area  Replacing the inverters by NAND gates with larger transistors resulted in a less than 1% area increase of the entire cache.

 The First observation: 37% 60%  The First observation: A way-concatenation cache results in an average energy savings of 37% compared to a conventional four-way cache, with savings over 60% for several examples. 284%  Compared to a conventional direct mapped cache, the average savings are more modest, but the direct mapped cache suffers large penalties for some examples – up to 284%  The second observation: way-concatenation way-shutdown %  The second observation: way-concatenation is better than way-shutdown for reducing dynamic power. It saves more energy sometimes saving %

way-shutdown  Although way-shutdown increases the miss rate for some benchmarks, for other benchmarks, way shutdown has negligible impact. gated-Vdd.  To save static energy, involving a circuit level technique called gated-Vdd. gated-Vdd  When the gated-Vdd transistor is turned off, the stacking effect of the extra transistor reduces the leakage energy dissipation.

 To save dynamic power:  To save dynamic power: A configurable cache design method called way-concatenation was developed. It saves 37% compared to a conventional four-way set-associative cache  To save static power:  To save static power: Extended the configurable cache to include a way-shutdown method, with average savings of 40%.

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