DRAM Tutorial Lecture Vivek Seshadri

Vivek Seshadri – Thesis Proposal DRAM Module and Chip 2

Vivek Seshadri – Thesis Proposal Goals Cost Latency Bandwidth Parallelism Power Energy 3

Vivek Seshadri – Thesis Proposal DRAM Chip 4 Row Decoder Array of Sense Amplifiers Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O

Vivek Seshadri – Thesis Proposal Sense Amplifier 5 enable top bottom Inverter

Vivek Seshadri – Thesis Proposal Sense Amplifier – Two Stable States V DD Logical “1” Logical “0”

Vivek Seshadri – Thesis Proposal Sense Amplifier Operation 7 0 VTVT VBVB V T > V B 1 0 V DD

Vivek Seshadri – Thesis Proposal DRAM Cell – Capacitor 8 Empty State Fully Charged State Logical “0”Logical “1” 1 2 Small – Cannot drive circuits Reading destroys the state

Vivek Seshadri – Thesis Proposal Capacitor to Sense Amplifier V DD 1 0

Vivek Seshadri – Thesis Proposal DRAM Cell Operation 10 ½V DD 01 0 V DD ½V DD +δ

Vivek Seshadri – Thesis Proposal DRAM Subarray – Building Block for DRAM Chip 11 Row Decoder Cell Array Array of Sense Amplifiers (Row Buffer) 8Kb

Vivek Seshadri – Thesis Proposal DRAM Bank 12 Row Decoder Array of Sense Amplifiers (8Kb) Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O (64b) Address Data

Vivek Seshadri – Thesis Proposal DRAM Chip 13 Row Decoder Array of Sense Amplifiers Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O Row Decoder Array of Sense Amplifiers Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O Row Decoder Array of Sense Amplifiers Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O Row Decoder Array of Sense Amplifiers Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O Row Decoder Array of Sense Amplifiers Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O Row Decoder Array of Sense Amplifiers Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O Row Decoder Array of Sense Amplifiers Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O Row Decoder Array of Sense Amplifiers Cell Array Row Decoder Array of Sense Amplifiers Cell Array Bank I/O Shared internal bus Memory channel - 8bits

Vivek Seshadri – Thesis Proposal DRAM Operation 14 Row Decoder Array of Sense Amplifiers Cell Array Bank I/O Data 1 2 ACTIVATE Row READ/WRITE Column 3 PRECHARGE Row Address Column Address

RowClone Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. B. Gibbons, M. A. Kozuch, T. C. Mowry Vivek Seshadri

Vivek Seshadri – Thesis Proposal Memory Channel – Bottleneck Core Cache MC Memory Channel Limited Bandwidth High Energy

Vivek Seshadri – Thesis Proposal Goal: Reduce Memory Bandwidth Demand Core Cache MC Memory Channel Reduce unnecessary data movement

Vivek Seshadri – Thesis Proposal Bulk Data Copy and Initialization Bulk Data Copy Bulk Data Initialization srcdst val

Vivek Seshadri – Thesis Proposal Bulk Data Copy and Initialization Bulk Data Copy Bulk Data Initialization srcdst val

Vivek Seshadri – Thesis Proposal Bulk Copy and Initialization – Applications Forking Zero initialization (e.g., security) VM Cloning Deduplication Checkpointing Page Migration Many more

Vivek Seshadri – Thesis Proposal Shortcomings of Existing Approach Core Cache MC Channel src dst High latency ( 1046 ns to copy 4 KB) Interference High Energy ( 3600 nJ to copy 4 KB)

Vivek Seshadri – Thesis Proposal Our Approach: In-DRAM Copy with Low Cost Core Cache MC Channel dst High latency Interference High Energy src X X X ?

RowClone: In-DRAM Copy 23

Vivek Seshadri – Thesis Proposal Two Key Observations 24 Row Decoder Any operation on one sense amplifier can be easily performed in bulk Many DRAM cells share the same sense amplifier 1 2

Vivek Seshadri – Thesis Proposal Bulk Copy in DRAM – RowClone 25 ½V DD 01 0 V DD ½V DD +δ Data gets copied

Vivek Seshadri – Thesis Proposal Fast Parallel Mode – Benefits 26 LatencyEnergy Bulk Data Copy (4KB across a module) 1046 ns to 90 ns 3600 nJ to 40 nJ No bandwidth consumption Very little changes to the DRAM chip 11X74X

Vivek Seshadri – Thesis Proposal Fast Parallel Mode – Constraints Location constraint – Source and destination in same subarray Size constraint – Entire row gets copied (no partial copy) Can still accelerate many existing primitives (copy-on-write, bulk zeroing) Alternate mechanism to copy data across banks (pipelined serial mode – lower benefits than Fast Parallel)

Vivek Seshadri – Thesis Proposal End-to-end System Design Software interface –memcpy and meminit instructions Managing cache coherence – Use existing DMA support! Maximizing use of Fast Parallel Mode – Smart OS page allocation 28

Vivek Seshadri – Thesis Proposal Applications Summary 29

Vivek Seshadri – Thesis Proposal Results Summary 30