Timer Programming in Assembly and C Prepared By:

2 Inside Architecture of 8051 CPU On-chip RAM On-chip ROM for program code 4 I/O Ports Timer 0 Serial Port Figure 1-2. Inside the 8051 Microcontroller Block Diagram OSC Interrupt Control External interrupts Timer 1 Timer/Counter Bus Control TxD RxD P0 P1 P2 P3 Address/Data Counter Inputs

3 Timers /Counters The 8051 has 2 timers/counters: timer/counter 0 and timer/counter 1. They can be used as 1.The timer is used as a time delay generator. –The clock source is the internal crystal frequency of the An event counter. –External input from input pin to count the number of events on registers. –These clock pulses cold represent the number of people passing through an entrance, or the number of wheel rotations, or any other event that can be converted to pulses.

4 Timer 8051 timers use 1/12 of XTAL frequency as the input of timers, regardless of machine cycle. Because the input of timer is a regular, fixed- periodic square wave, we can count the number of pulses and calculate the time delay. to LCD P TL0 TH0 Set Timer 0 XTAL oscillator ÷ 12Timer

5 Counter Count the number of events External input from Tx input pin (x=0 or 1). We use Tx to denote T0 or T1. –External input from T0 input pin (P3.4) for Counter 0 –External input from T1 input pin (P3.5) for Counter 1 T0 to LCD P3.4 P a switch TL0 TH0 Vcc

6 Figure 9-8: Timer/Counter 0 XTAL oscillator ÷ 12 TR0 INT0 Pin Pin 3.2 C/T = 0 Gate T0 Pin Pin 3.4 C/T = 1 TH0TL0 TF0 1. monitor by JNB 2. interrupt timer input hardware control 1:start 0:stop counter input Sec 9.2  

7 Figure 9-9: Timer/Counter 1 XTAL oscillator ÷ 12 TR1 INT1 Pin Pin 3.3 C/T = 0 Gate T1 Pin Pin 3.5 C/T = 1 TH1TL1 TF1 1. monitor by JNB 2. interrupt 1:start 0:stop timer input counter input hardware control

8 Registers Used in Timer/Counter TH0, TL0 (Timer 0 registers) TH1, TL1 (Timer 1 registers) TMOD (Timer mode register) TCON (Timer control register) You can see Appendix H (pages ) for details. Since 8052 has 3 timers/counters, the formats of these control registers are different. –T2CON (Timer 2 control register), TH2 and TL2 used for 8052 only.

9 Basic Registers of the Timer Both Timer 0 and Timer 1 are 16 bits wide. –Each 16-bit timer can be accessed as two separate registers of low byte and high byte. –Timer 0: TH0 & TL0 Timer 0 high byte, timer 0 low byte –Timer 1: TH1 & TL1 Timer 1 high byte, timer 1 low byte –These registers stores the time delay as a timer the number of events as a counter

10 Timer Registers D15D8D9D10D11D12D13D14D7D0D1D2D3D4D5D6 TH0TL0 D15D8D9D10D11D12D13D14D7D0D1D2D3D4D5D6 TH1TL1 Timer 0 Timer 1

11 TCON Register (1/2) Timer control register: TCON –Upper nibble for timer/counter, lower nibble for interrupts TR (run control bit) –TR0 for Timer/counter 0; TR1 for Timer/counter 1. –TRx is set by programmer to turn timer/counter on/off. TRx=0: off (stop) TRx=1: on (start) TF1TR1TF0TR0IE1IT1IE0IT0 Timer 1 Timer0for Interrupt (MSB)(LSB)

12 TCON Register (2/2) TF (timer flag, control flag) –TF0 for timer/counter 0; TF1 for timer/counter 1. –TFx is like a carry. Originally, TFx=0. When TH-TL roll over to 0000 from FFFFH, the TFx is set to 1. TFx=0 : not reach TFx=1: reach If we enable interrupt, TFx=1 will trigger ISR. TF1TR1TF0TR0IE1IT1IE0IT0 Timer 1 Timer0for Interrupt (MSB)(LSB)

13 Table 9-2: Equivalent Instructions for the Timer Control Register For timer 0 SETB TR0=SETB TCON.4 CLR TR0=CLR TCON.4 SETB TF0=SETB TCON.5 CLR TF0=CLR TCON.5 For timer 1 SETB TR1=SETB TCON.6 CLR TR1=CLR TCON.6 SETB TF1=SETB TCON.7 CLR TF1=CLR TCON.7 TF1IT0IE0IT1IE1TR0TF0TR1 TCON: Timer/Counter Control Register

14 TMOD Register Timer mode register: TMOD MOV TMOD,#21H –An 8-bit register –Set the usage mode for two timers Set lower 4 bits for Timer 0 (Set to 0000 if not used) Set upper 4 bits for Timer 1 (Set to 0000 if not used) –Not bit-addressable GATEC/TM1M0GATEC/TM1M0 Timer 1Timer 0 (MSB)(LSB)

15 Figure 9-3. TMOD Register GATE Gating control when set. Timer/counter is enabled only while the INTx pin is high and the TRx control pin is set. When cleared, the timer is enabled whenever the TRx control bit is set. C/T Timer or counter selected cleared for timer operation (input from internal system clock). Set for counter operation (input from Tx input pin). M1 Mode bit 1 M0 Mode bit 0 GATEC/TM1M0GATEC/TM1M0 Timer 1Timer 0 (MSB)(LSB)

16 C/T (Clock/Timer) This bit is used to decide whether the timer is used as a delay generator or an event counter. C/T = 0 : timer C/T = 1 : counter

17 Gate Every timer has a mean of starting and stopping. –GATE=0 Internal control The start and stop of the timer are controlled by software. Set/clear the TR0 (or TR1) for start/stop timer. –GATE=1 External control The hardware way of starting and stopping the timer by software and an external source. Timer/counter is enabled only while the INT0 (or INT1) pin has an 1 to 0 transition and the TR0 (or TR1) control pin is set. INT0: P3.2, pin 12; INT1: P3.3, pin 13.

18 M1, M0 M0 and M1 select the timer mode for timers 0 & 1. M1 M0 Mode Operating Mode bit timer mode 8-bit THx + 5-bit TLx (x= 0 or 1) bit timer mode 8-bit THx + 8-bit TLx (x= 0 or 1) bit auto reload 8-bit auto reload timer/counter; THx holds a value which is to be reloaded into TLx each time it overflows Split timer mode

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