lab5-1 張明峰 交大資工系 Lab 5: FSM and BCD counters Implement the vending machine of lab 2 A two-digit BCD counter –two BCD counters –can load data in parallel

lab5-2 張明峰 交大資工系 Vending Machine module machine (ti,fi,out,state,rst); output out; output [1:0] state; input ti,fi; input rst; reg [1:0] state,nextstate; reg t1,t2,f1,f2;

lab5-3 張明峰 交大資工系 Vending Machine BUFG g1 (.O(clk_hi),.I(clki)) ; BUFG g2 (.O(clk),.I(clk_sl)) ; (posedge clk_hi) cnt = cnt +1 ; assign clk_sl = (cnt >= 15’h4000) ; assign out = (state == 3); (posedge clk) begin t2 = t1 ; t1 = ti ; f2 = f1 ; f1 = fi ; end assign t = t1 & ~t2 ; assign f = f1 & ~f2 ;

lab5-4 張明峰 交大資工系 Vending Machine or f ) case(state) 0: begin if (f) nextstate = 1; else if (t) nextstate = 2; else nextstate =0; end 1: begin if (f) nextstate = 2; else if (t) nextstate = 3; else nextstate =1; end

lab5-5 張明峰 交大資工系 Vending Machine 2: begin if(f) nextstate = 3; else if(t) nextstate = 3; else nextstate =2; end 3: nextstate = 0; endcase endmodule

lab5-6 張明峰 交大資工系 Global Clock Buffers Clock Buffers are low-skew, high drive buffers –Also known as Global Buffers –Drive low-skew, high-speed long line resources –Drive all Flip-Flops and Latches in FPGA –Can also be used for high-fanout signals Instantiation: if the BUFG component is instantiated, software will select one of these buffers based on the design –BUFG u1 (.I(clki),.O(clk)) ;

lab5-7 張明峰 交大資工系 IOBs Organized As Independent Banks As many as eight banks on a device –Package dependent Each bank can be assigned any of the 16 signal standards XC2S50 PQ208 –GCK 0: pin 80 –GCK 1: pin 77 –GCK 2: pin 182 –GCK 3: pin 185

lab5-8 張明峰 交大資工系 4-bit binary counter w/ parallel load

lab5-9 張明峰 交大資工系 async count load' load c_en c_en A 0

lab5-10 張明峰 交大資工系

lab5-11 張明峰 交大資工系 Generate any count sequence: –E.g.: BCD counter  Counter w/ parallel load

lab5-12 張明峰 交大資工系 A synchronous 4-bit binary counter with an asynchronous Clear is used to make a Modulo 7 counter. Use the Clear feature to detect the count 7 and clear the count to 0. This gives a count of 0, 1, 2, 3, 4, 5, 6, 7(short)0, 1, 2, 3, 4, 5, 6, 7(short)0, etc. DON ’ T DO THIS! Referred to as a “ suicide ” counter! (Count “ 7 ” is “ killed, ” but the designer ’ s job may be dead as well!) Counting Modulo 7: Detect 7 and Asynchronously Clear Clock 0 D3 Q3 D2 Q2 D1 Q1 D0 Q0 CLEAR CP LOAD

lab5-13 張明峰 交大資工系 A synchronous 4-bit binary counter with a synchronous load and an asynchronous clear is used to make a Modulo 7 counter Use the Load feature to detect the count "6" and load in "zero". This gives a count of 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 0,... Using don ’ t cares for states above 0110, detection of 6 can be done with Load = Q4 Q2 Counting Modulo 7: Synchronously Load on Terminal Count of 6 D3 Q3 D2 Q2 D1 Q1 D0 Q0 CLEAR CP LOAD Clock Reset

lab5-14 張明峰 交大資工系 A synchronous, 4-bit binary counter with a synchronous Load is to be used to make a Modulo 6 counter. Use the Load feature to preset the count to 9 on Reset and detection of count 14. This gives a count of 9, 10, 11, 12, 13, 14, 9, 10, 11, 12, 13, 14, 9, … If the terminal count is 15 detection is usually built in as Carry Out (CO) Clock D3 Q3 D2 Q2 D1 Q1 D0 Q0 CLEAR CP LOAD Counting Modulo 6: Synchronously Preset 9 on Reset and Load 9 on Terminal Count 14 Reset 1

lab5-15 張明峰 交大資工系 BCD Counter Function table TC = 1, if Q== 9; otherwise, TC = 0 asyn_rstclk_enclkloadfunction 0XXXreset 1Xposedge1load 10posedge0hold 11posedge0count

lab5-16 張明峰 交大資工系 A two-digit BCD counter –two synchronous BCD counters –two 7-segment decoders