הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Modeling and Optimization of VLSI Interconnect 049031 Lecture 4: Interconnect modeling Avinoam Kolodny Konstantin Moiseev VLSI-מודלים ואופטימיזציה של קווי חיבור ב

הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Outline Delay modeling – continuation Elmore delay for general input Model reduction. Asymptotic Waveform Evaluation. Moments calculation Two-pole model example Delay metrics based on moments. Transition time modeling Central moments and their relation to moments Representation of response as a probability distribution. Alpert estimation for receiver slope. Slope expressions based on moments Explicit output slope calculation for singe RC-stage Driver-receiver interaction Driver modeling. K-equations Admittance and impedance calculations Representation of load as “PI-model”. Effective capacitance and algorithm for its calculation. Two-step delay approximation VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Asymptotic Waveform Evaluation (AWE) הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Asymptotic Waveform Evaluation (AWE) Elmore delay uses first moment to represent system response Not very accurate For more accurate estimation, more moments are required AWE uses moments matching to calculate parameters of low-order model: where the reduced order is much less than the original order AWE flow: Generate moments from the circuit Match the first moments to low-order pole model Calculate residues Obtain time-domain response by inverse Laplace transform “Asymptotic waveform evaluation for timing analysis”, L. Pillage and R. Rohrer, 1990 VLSI-מודלים ואופטימיזציה של קווי חיבור ב

הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Calculating moments How to calculate moments without knowing transfer function? From circuit theory: RC-tree solution can be represented by: Represent: Then Initial excitation vector Conductance and capacitance matrices Node voltages (unknowns) vector G includes resistances and inductances X is node voltages for capacitances and current sources and currents for inductances and voltage sources E is voltages for inductances and voltage sources and currents for capacitances and current sources Matching coefficients VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Calculating moments First equation meaning: Second equation meaning: Solve system for DC ( ) with the original excitation I.e. all capacitors are open-circuited and node voltages are calculated Second equation meaning: Solve system for DC ( ) with the original excitation is set to zero, a new excitation is applied instead and node voltages are calculated I.e. moments are calculated recursively For calculation For calculation

Moments calculation example הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Moments calculation example All caps are 1F All resistances are 1Ω Input voltage is 1V Moment 0: all capacitances are open circuited Moment 1: all capacitances are replaced by current sources and input is grounded Generally, one of unknowns is voltage source current, and its moments are calculated also. It is not shown in the vector of moments VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Example: two-pole approximation Assume we calcuated moments of the circuit: Transfer function for reduced model: Cross-multiply: Coefficient match: Build as many equations as needed to resolve all unknowns In this case only 4 moments are required

Example: two-pole approximation All caps are 1F All resistances are 1Ω Input voltage is 1V Moments at node 5 are: 1, -10, 85, -707, …

AWE pros and cons Allows simplification of the model Pretty accurate Reduced model representation in memory is compact No exact formula for roots of polynomial with degree higher than 4 Using numerical methods – computationally expensive Higher-order AWE approximations are often unstable Meaning positive poles Special methods are needed

Some delay expressions based on first two moments הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Some delay expressions based on first two moments “An analytical delay model for RLC interconnects”, A.B.Kahng and S.Muddu, 1997 two pole, two moments “Accurate analytical delay model for VLSI interconnects”, A.B.Kahng and S.Muddu, 1995 one pole, matching second moments instead of first D2M metric: the factor m1/sqrt(m2) was found to be much less than one for near-end nodes and slightly greater than one for far-end nodes. On the other hand, scaled Elmore (single pole approx.) significantly overestimates delay at the near-end, while slightly underestimate delay at the far end Say that there are also many others – fitting to beta function, lognormal function etc. “RC delay metrics for performance optimization”, C.J. Alpert, A. Devgan and C.V. Kashyap, 2001 “D2M metric” pure empirical VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Central moments Elmore was the first who made a comparison between voltage derivative waveform and PDF Keeping this analogy higher-order waveshape terms can be characterized by central moments Central moments of the impulse response are the moments about the mean:

Understanding central moments הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Understanding central moments Zero moment is the area under the curve. Usually 1 First moment the mean deviation around mean, thus it is 0 Second moment is the variance of the distribution Third moment is the skewness of the distribution Distribution is symmetric if median mean mode Central moments have important geometrical meaning VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Some important properties Second and third central moments add under convolution, i.e. for holds that: Second and third central moments are always positive

Elmore delay for general inputs The real input is not a step voltage It is modeled usually by saturated ramp Following results hold: For an RC circuit with monotonically increasing, piecewise-smooth input such that is a nonnegatively skewed unimodal function, holds for the output response at any node. For an RC circuit with monotonically increasing, piecewise-smooth input such that is a symmetric function, then the Elmore delay of the output response reaches 50% delay as the rise-time of input signal reaches infinity. The area between input and output response equals Elmore delay. For saturated ramp:

Ramp follower When input signal transition time is large, transient response is negligible Such kind of response is called ramp follower In ramp follower, Elmore delay is almost exact delay metric Real circuit example

Another example – lumped RC circuit

Transition time modeling Transition time: requires calculation of two points Usually less accurate Recall: Again Elmore proposal… Transition time is proportional to second central moment!!

Slew rate for step input Assume step response modeled by single time constant: Impulse response is therefore: Second central moment for this distribution is: Now, match second central moment of model and actual circuit to find : “A simple metric for slew rate of RC circuits based on two moments”, Agarwal, Sylvester, Blaauw, 2004

Slew rate for step input הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Slew rate for step input To find 10%-90% slew rate, substitute back to step response and obtain: Works good for far-end nodes For near-end nodes single pole apporximation fails Better metric is found empirically: S2M metric scaled S2M metric Matching just the first moment we obtain dominangt pole approximation - good for delay, not for slew Bakoglu proposed metric of ln(9)*Elmore, based on first moment only From D2M Example: VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Extension for ramp inputs We know that for LTI system holds: According to convolution property: And since , we can write: We have: Recall: second central moments are added after convolution of two PDFs !!! is a PDF of step response is a PDF of input waveform is a PDF of output waveform “Closed form expressions for extending Step Delay and Slew Metrics to Ramp Inputs”, Kashyap, Liu, Alpert, Devgan, 2003

Extension for ramp inputs Therefore Taking Elmore assumption that slew rate is proportional to standard deviation: And therefore: Assuming all constants are equal we get: PERI – PDF Extension to Ramp Inputs

Extension for ramp inputs We get: In other words, the output slew rate is the root-mean square of the input signal slew and step response skew. Example: lumped RC circuit for Exact calculation gives Using PERI: Area 1 Area 2

Using PERI for delay estimation הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Using PERI for delay estimation Using PERI, the following expression is obtained for 50% delay: where If , then and Elmore Without proof VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Interacting with gate delay models Interconnect does not exist standalone Usually we want to calculate stage delay / slew rather than pure interconnect delay / slew The problem: Interconnect is linear system Gate is not ! To model stage delay / slew we need: Develop simple and accurate gate model Be able to combine gate and interconnect models without loss of accuracy input waveform output waveform stage

Gate modeling How to model non-linear gate? First option – switch resistor model (i.e. linear model) Advantage: Is able to capture the interaction of the gate’s output resistance and the RC load Disadvantages: Requires calculating a single linear resistor that captures the switching behavior of CMOS gate Neglects effecy of the input transition time on delay

הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM K-factor equations Model delay and output transition time as functions of capacitive load and input transition time For example: All parameters are set empirically k-factor equations Can use more than one point for input waveform or more complicate load model Input waveform is modeled by saturated ramp (single number) VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Table-lookup model Empirical models usually do not scale well Preferred approach is pre-characterize each cell for bunch of input transitions and output loads Exact value for specific inputs is found using interpolation This approach requires two two-dimensional tables (delay and output slew) for each in-out cell transition

Two–step delay approximation For non-linear gate model the delay and slew at stage outputs is calculated in two steps: Given input slew and driver load, delay and slew at the gate output are calculated from gate model (either empirical or table-based). Gate output waveform is approximated by saturated ramp The delay and the slew at the interconnect output are calculated using interconnect model with given sturated ramp input Should take into account gate non-linearity Linear interconnect model

Handling cell load Cell output is loaded by interconnect tree The characterization expects single load capacitance number For pure capacitive interconnect the characterization will work as is Can use as a load It will not work for resistive interconnect !!! The solution: map complex load to single effective capacitance Allows using table-lookup model Handles complex interconnect structure

Effective capacitance

Calculating Effective capacitance itself is calculated in two stages: RC-tree is reduced to two-pole model is calculated iteratively by comparing average current drawn from a source by model and by single capacitance up to 50% delay point

Representing RC load by model הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Representing RC load by model Recall from circuit theory: Input admittance is defined by Input admittance represents “load” seen by external source connected to the system input Admittance moments: Should emphasize that we need to represent load, therefore we look at admittance rather than transfer function There is only one admittance for the whole RC-tree (at root), unlike transfer functions VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Representing RC load by model הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Representing RC load by model On the other hand, model admittance is given by: Matching admittance moments we have: Solving system obtain: O’brien-Savarino reduction Notice locations of C1 and C2 VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Constructing Thevenin model הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Constructing Thevenin model Thevenin model (non-constant voltage source + resistance) is used to model input waveform VLSI-מודלים ואופטימיזציה של קווי חיבור ב

Iterative Ceff calculation process

Backup

Some RC-tree system definitions Input admittance: Input impedance: (voltage) Transfer function:

הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה 1:56:27 AM Modeling distributed RC-line is too complicate even for single point-to-point line Interconnect is usually represented by RC-tree Easily computable and accurate interconnect model is required (delayout; slopeout) (delayout; slopeout) (delayin; slopein) (delayout; slopeout) VLSI-מודלים ואופטימיזציה של קווי חיבור ב