Amitava Roy VECC

 Mostly towards the in-house experimental nuclear physics program  Little participation towards CBM-FAIR  Data Acquisition Software development and System design  Relevant utility hardware development  Digital Pulse Processing technique  Beam-diagnostics and computer control  Other activity – Application of Neural Network, Ant Colony Optimization, Parallel Computation, Gamma Camera Development

Requirement Analysis Interaction with the user groups System Design Architecture Selection Read out System Selection – CAMAC/VME Throughput Estimation Procurement Previously  Procurement for system development and users system Presently  Procurement for system development only Data Acquisition Activities at VECC

Software Development Application software development : CAMAC and VME  OS Platform: SINTRAN-III (Old), Windows and Linux Esone Library Development for CAMAC Linux Driver development for CAMAC Data Acquisition Activities at VECC (contd.) System Integration, Testing, Release Application Software is integrated with representitive hardware Extensive Lab testing is carried out with Pulser (Precision and Random) and Radioactive Sources Field testing by users for feed back and released to the users Software Support All the software developed by us on Windows and Linux for VME as well as CAMAC are upgraded as and when required and supported through out their life cycle

Structure of VMEDAQ Software and New CAMAC Software CONTROLLER LPADCs CAMAC BUS VME CONTROLLER ADCs VME BUS QDCs PCI Interface CAMAC Device Driver / lib VME Device Driver / lib module_base CAMAC V785 V792 READ Loop PollingBlock Read Buffer0 Buffer1 Event Generator Buffer0 Buffer1 Process loop 1D 2D if 1D User Interface Associator Control Data & control Function list Event Handler Mouse Keyboard 1D Histogram 2D Histogram 1D Histogram

Electronic Setup (DAQ + Electonics) kept at experimental hall, Monitored remotely from the control room. VME based Data Acquisition System developed at VECC has been used for event by event mode data store. 16 channels PreAmp Scattering Chamber Experimental Setup:

Hardware Development CAMAC Crate Controller Trigger Module NIM-CAMAC interfaces SCALER General Purpose, Neutron multiplicity counter Pulse Generator Synchronizer for multi crate operation Development towards CBM experiments FPGA based high end read out controller cards for nXYTER 27 Numbers already supplied to MUCH group at VECC

A Customized CAMAC SCALER for Neutron Multiplicity Counting The module counts pulse coming out from neutron detector for each event The pulses are GATED by experiment logic for a fixed width for each event The module generates Look-At-Me (LAM) at the trailing edge of each event The LAM can initiate reading out of the neutron multiplicity count as one of the parameters in the list mode The counter is cleared after each readout Further GATE is blocked till the counter is cleared The random partial effective GATE width resulted due to the statistical occurrence of event asynchronous with respect to the module ‘CLEAR’ is eliminated with customized logic. The above customization is essential to get proper neutron multiplicity distribution The module can also be operated as a normal Gated 4-ch 16-bit SCALER or 2-ch 32 bit SCALER by changing mode

ROC Board: Production & Tests FX20 Qty:2 January,2010 FX60 Qty:1 November,2010 FX40 Qty:2 June,2011 FX40 Qty:8 November,2011 Fx40 Qty:14 December,2011 Read out Controller board for CBM MUCH · FPGA: Xilinx Virtex-4 FX Series · Storage for embedded processors: · SDRAM: Two 64 MByte DDR1, 16 bit interface to Flash · Communication Interfaces · RS232 · USB 1.1 · 0/100 MBit Ethernet · 2.5 Gb optical link

ASIC based design initiatives : Prototype card development for Si-strip detector signal processing with commercially available ASIC VA32 and TA32 from IDE AS FEE Card Layout with VA32HDR and TA 32 CG Micro-controller based testing card VA32 HDR foot printTA32 CG foot printZoom of the Wire-bond portion

Currently on going Activities on DAQ Digital Filter based acquisition system – R & D stage Best Result so far ~ 5Kev (0.37 %) compared to Analog system 1.8 KeV (0.14 %)

Currently on going Activities on DAQ (Contd.) Detector Array A Detector Array B Trigger A Trigger B Global Time DAQ A DAQ B Event Builder Several Data Acquisition System Autonomous trigger: Integrating Heterogeneous DAQ

 It is an advanced search and sorting algorithm to construct the offline global event from large amount of stimulated time-stamped data set of VME/CAMAC events.  It provides an elegant solution to the problem when the file sizes exceed the capacity of main memory by the creation of lazy data structures which can hold an infinite number of items by performing an on-demand reading of data from disk to memory. The VME/CAMAC events are read in as “blocks” from the files in secondary storage. Following steps are performed to merge the k number sequence (or external files of lengths n1, n2… nk) to generate a single sorted merged sequence of total length n (where n = n1 + n2+ … nk) using the min-heap. Step-1: Every first element (which is the smallest element) from each sorted sequences are removed and builds a min-heap (or a min-priority queue). Then the following steps are repeated until the min-heap is empty. Step-2(a): The minimum element from the min-heap is extracted which will be the next element in the sorted order is stored in a global event sequence. Step-2(b): The next smallest element from the original sorted sequences where this element came from is removed (if it exists) and inserted to the min-heap. At this point sorted merged sequence is formed which is stored back to the disk as an offline global event. The time complexity of this implementation is observed to be O(n log k).

Available Skill Set in the DA & CC Division Languages : C, C++, Visual Basic, JAVA,C#,F# GUI: VB, Win-SDK, Qt, JAVA, MEDM Parallel Processing: OpenMP, MPI SCADA: LABView, EPICS OS: Windows, Linux, Micro-linux Life Cycle Tool: Rational ROSE EDA Tools: Xilinx, ALDEC, SPICE Analog Design: Nuclear and other FAST Electronics, Opto-electronics, Motor drives Digital Design: Digital Logic Design, FPGA, Microprocessors including ARM, FPGA Soft- core processor

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