Analog IC design 1주차 Sept.25th.

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Presentation transcript:

Analog IC design 1주차 Sept.25th

My cad review My cad 실행 MyCAD Pro 2007 > LayEd Pro Layout 편집 프로그램 Schematic과 Layout 비교 프로그램 회로 해석 위한 SPICE 프로그램

My cad review Technology Path에 Technology file 선택

My cad review Project Path Technology Path Create a folder on the desktop which is named your ID number Create the project file, for example “xxx.prj” Technology Path MyCADPro > Demo > IDS > Mycell < Layout folder ` SCMOS_SCN4ME_SUBM.TEC’ file

My cad review Execute ‘New Cell’ Insert the layout name on “Cell Name”

My cad review Bind Library C:\MyCADPro\Demo\IDS\MyCell\Layout\Mycell.prj

How to use Mycad Bind된 Library Tec파일에 포함된 layer 디스플레이

My cad review – layer 설명 노드에 마커 찍는것처럼 인덱스 표시할 때 텍스트 사용 Nwell Defines well of p-channel devices. Metal3 Defines third metal interconnects. Active Defines N+, P+ active and n-ch, p-ch gate areas Via3 Defines openings in insulator between metal 3 & 4. Poly Defines poly gates and poly interconnects., poly silicon Metal4 Defines fourth metal interconnects. Nplus Defines N+ area Glass Pplus Defines P+ areas Probe Poly2 Defines Capacitor areas Res_mask Resistor mask Contact Defines contact metal1 to active & poly. Polytxt Poly text via Defines opening in insulator between metal1 & 2. Me1txt Metal1 text metal1 Defines first metal interconnects. Me2txt Metal2 text metal2 Defines second metal interconnects. me3txt Metal3 text 노드에 마커 찍는것처럼 인덱스 표시할 때 텍스트 사용

시작하기 전 검은 바탕은 기본적으로 P-SUBSTRATE를 의미 P-SUBSTRATE는 Ground 쪽에 가까워야하고 n-well은 VDD 쪽에 가까워야 한 다. (p-well 사용시 반대) 따라서 P-SUB에 Ground를 연결해주어야 Electric Rule Check시 error가 뜨지 않음 Inverter의 nmos에 연결되있는 bulk를 빈 셀의 p-substrate에 복사한다.

Resistor layout Poly resistor Poly resistor - layout 만약 Sheet Resistance가 20Ω, Square수가 6이라면 저항은 120Ω Square 1개 Poly resistor - layout Metal과 poly가 만나는 곳에 contact Resistor Mask 시트 레지스턴스를 알면 칸의 개수를 가지고 저항 값을 추측할 수 있음 GND 연결 W … L

Resistor DRC(Design Rule Check) ERC(Electrical Rule Check) MyCAD Pro > Demo > IDS > MyCell > Layout > Layout Verification Rule > CMOS_SCN4ME_SUBM_DRC.rul ERC(Electrical Rule Check) Layout Verification Rule > CMOS_SCN4ME_SUBM_ERC.rul DRC, ERC가 활성화되어 있지 않은 경우 저장 후 실행

Resistor ERC 후 netlist(회로 연결 정보) 추출 결과 저항의 Width, Length

Report (due date 10/2) Calculate Sheet Resistor. Design high resistor1kΩ Using series connection. Series connection is wired by metal1. Think about making high resistor. Tool 사용 Tip. Ruler (K) Zoom In/Out (+/-) Error non-display (H) Layer Window에서 사용할 layer를 선택하고 를 누르면 그리기 가 활성화