PCI 9052 소개 권 동혁

Contents 1.Introduction 2.Major features 3.PCI 9052RDK-LITE

1. Introduction PLX Technology, Inc. PCI 9052 – 어댑터 보드용 compact, high-performance PCI bus target(slave) interface 제공 –ISA(Industry Standard Architecture) 어댑터를 저렴한 비용으로 신속하게 PCI 버스로 변환 – 어댑터 보드 상에서의 I/O data 이동 속도를 ISA 의 공식 bus 속도인 8MHz, 5MB/sec 에서 PCI 의 33MHz, 132MB/sec data 전송 속도로 가속 –Applications : networking, telecommunication, imaging, industrial, storage

2. Major features  32-bit, 33MHz PCI r2.1 compliant  Direct slave (target) data transfer mode -Supports burst memory-mapped and single I/O-mapped accesses from the PCI-to-Local bus -Read and write FIFO : enables bursting on the local & PCI buses -PCI bus = always bursting, Local bus= bursting or continuous single cycle.  ISA interface mode logic on board - Supports single cycle reads/writes for 8-, 16-bit memory and I/O- mapped accesses from the PCI Bus to ISA bus  Interrupt generator - generate a PCI interrupt from 2 local bus interrupt inputs, or by software writing to an internal register bit

 Clock -runs from a local TTL-compatible clock and generates the necessary internal clocks. -Internal clock : PCI clock 과 비동기 동작, local bus 가 PCI clock 과 독립적으로 동작.  Programmable local bus configurations -Supports multiplexed and non-multiplexed 8-, 16-, and 32-bit generic local buses -Non-multiplexed mode : 4 Local Byte Enable (LBE[3:0]#), 26 address lines (LA[27:2]), 32,16, or 8 data lines (LAD[31:0]) -Multiplexed mode : 4 Local Byte Enable (LBE[3:0]#), 28 address lines (LAD[27:0]), multiplexed with 32,16, or 8 data lines (LAD[31:0])

 Direct slave read ahead mode -Prefetched data can be read from the internal FIFO instead of the local bus. -Address : 연속적인 32-bit aligned (next address = current address+4)  Bus drivers - All control, address, data signals generated by the PCI 9052 directly drive the PCI and Local buses without external drivers.  Serial EEPROM interface -contains a three-wire serial EEPROM interface that provides the option of loading configuration information from a serial EEPROM device. - Note: A serial EEPROM is required when ISA Interface mode is selected.

 4 local chip selects -Provides up to four local chip selects. -The base address and range of each chip select are independently programmable from the serial EEPROM or Host.  Five Local Address Spaces -The base address and range of each local address space are independently programmable from the serial EEPROM or Host.  Big/Little Endian Byte Swapping -Supports Big and Little Endian byte ordering.  Local Bus Wait States - PCI 9052 has an internal wait state generator (Read and Write address-to-data, data-to-data, and data-to-address).

 Read/Write Strobe Delay and Write Cycle Hold -Read and Write strobe (RD# and WR#, respectively) timings can be programmed independently for each Local Address Space.  Programmable Prefetch Counter -The Local Bus Prefetch Counter can be programmed to 0 (no prefetch), 4, 8, 16, or Continuous (Prefetch Counter turned off) Prefetch mode. -The prefetched data can be used as cached data if a consecutive address is used (must be Lword- aligned).  Direct Slave Delayed Read Mode - supports PCI r2.1 Delayed Read with: PCI Read with Write Flush mode PCI Read No Flush mode PCI Read No Write mode PCI Write Release Bus mode

 PCI Read/Write Retry Delay Timer - The PCI 9052 has a programmable Direct Slave (PCI Target) Retry Delay timer, which, when expired, generates a Retry to the PCI Bus.  PCI LOCK Mechanism. - Supports Direct Slave LOCK sequences. A PCI Master can obtain exclusive access to the PCI 9052 device by locking to the PCI  PCI Bus Transfers up to 132 MB/s.  Low-Power CMOS in 160-pin Plastic QFP Package (PQFP)

registers

ISA interface mode –Performs only single cycles to ISA interface memory and I/O. –Does not support ISA bus master transfer nor ISA DMA. –LAS0RR  Memory command access –LAS1RR  I/O command access –LCLK : 8MHz external clock input –INTCSR[12]=1:ISA interface mode enable. set by serial EEPROM * PIN definitions

Serial EEPROM After reset, PCI 9052 attempts to read the serial EEPROM The first 48 bits are not all (1) : continues reading PCI 9052 generates the EEPROM clock by internally dividing the PCI clock by 32. Serial EEPROM initialization completes in approx.780 ㎲, with a 33.3MHz PCI clock.

3. PCI 9052RDK-LITE Flexible Rapid Development Kit for designs using the PLX PCI 9052 PCI bus target device. Features - PLX PCI 9052 PCI bus target interface chip with direct ISA interface -ISA bus interface connector -Socketed serial EEPROM for PCI 9052 configuration -Support for 16-bit ISA and 32-bit multiplexed and non-multiplexed local bus modes -CPLD with spare capacity for additional prototyping logic -28 surface-mount QFP/PLCC footprints and ” BGA landscape for memory, FIFO, I/O devices, logic devices, etc. -32-pin PLCC socket for expansion ROM -On-board 128KB of SRAM and associated logic for PCI 9052 continuous burst read/write accesses -Socketed 32MHz oscillator for local bus clock -5V to 3.3V voltage regulator -6 logic analyzer headers with standard HP footprint to allow easy probing of local bus signals -25*25, 0.1 ” through-hole prototyping grid

RDK Hardware Architecture

ISA to PCI Migration ( 예시 ) Assume : the ISA card requires 1K bytes of memory space starting at address 0x1000h on the ISA bus and 16 bytes of I/O space starting at address 0x308h 1.ISA Memory Mapping 1)1K bytes:0~0x3ffh  inverse : 0xfffffc00h  LAS0RR 2)base address(0x1000h):0x h  LAS0BA (the base address is a multiple of the range. No need to modify. LSB:1  enable the local address space) 2. ISA I/O Mapping * The base address is not a multiple of the range.  reduce the base address value, increase the range to compensate. 1)lower the base address to 0x300h : 0x h  LAS1BA 2)increase the range to 32 bytes  0x1fh. 0xffffffe1h  LAS1RR (LSB:1  local address space 1 is mapped into I/O space)

3. Chip select configuration (CS0~3BASE) 1) memory mapped region in local address space 0 : CS0BASE  0x h 2) I/O mapped region set up in local address space 1 : CS1BASE  0X h 4. Other Local Settings 1)Bus Region Descriptor (LAS0~3BRD) - 8 bit ISA operation : 0x h  LASxBRD - 8-bit ISA,pre-fetch disabled: 0x h  LASxBRD (default:pre-fetching disabled for both ISA memory & I/O) 2)Initialization Control Register (CNTRL) - CNTRL  0x007X0X12h (X : specific adapter 의 해당 값 ) ( PCI v2.1 compatible system : [14]=1, [22:19]=don ’ t care) 3)Interrupt Control/Status Register ( INTCSR) - INTCSR  0x1XXXh ([12]=1 : ISA bus mode) - if interrupts are desired, enable the appropriate local interrupts in the INTCSR register and also enable the PCI interrupt(INTCSR[6])

5. Interrupts * ISA card : jumpers to select the appropriate IRQ * PCI : only one interrupt INTA#, shared between other PCI devices. * ISA card IRQ  one of the PCI9052 interrupt line(LINTix) (INTCSR enable 되어 있으면 PCI INTA# signal 발생 ) 6. Serial EEPROM - A serial EEPROM is required when using PCI9052 in ISA mode. The EEPROM must be used to set all the local registers. 7. PCI Access to local ISA BUS - PCRBAR0,1 : addresses of the PCI 9052 in the PCI memory & I/O - PCRBAR2,3 : addresses in the PCI memory & I/O spaces that are mapped to the ISA memory and I/O spaces. ex) Local address space 0=memory mapped 0x h ~..13ffh Local address space 1=memory mapped 0x h ~..13ffh Assume the BIOS places : PCIBAR2=0xffcf0000h, PCIBAR3=0x0000fc01h  addressing 0xffcf0014h  access on the local bus at 0x h addressing I/O location 0x0000fc08h  access on local bus 0x308h