ATLAS Lar Calorimeter trigger electronics phase I upgrade LDPB Firmware Development Environment (ABBA, LATOME) 1.

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Presentation transcript:

ATLAS Lar Calorimeter trigger electronics phase I upgrade LDPB Firmware Development Environment (ABBA, LATOME) 1

2 Revision history VersionDateAuthorDescription 0.114/01/2015Nicolas ChevillotFirst draft 0.203/03/2015Nicolas Chevillot 0.301/06/2015Nicolas ChevillotUpdated with latest changes

Agenda Description of ABBA/LATOME(AMC) working group Description of development environment ▫ e-group ▫ JIRA project ▫ GIT repository ▫ Simulation and compilation 3

ABBA/LATOME(AMC) working group Multiple projects  Have a common environment for all projects Developers spread across the world ▫ CPPM/LAPP (France) ▫ University of Dresden (Germany) ▫ University of Tokyo (Japan) ▫ University of Arizona (USA) ▫ Budker INP and Novosibirsk State University (Russia)  Need to have a way to share code Developers organized in teams working on dedicated parts of the design  Need to be able to protect areas of code 4

Development environment CERN provides multiple tools ▫ JIRA project ▫ GIT repositories Can be accessed from anywhere 5 atlas-lar-ldpb-firmware GIT repository Remote computer(s) Local computer(s) Registered member of atlas-lar-ldpb- firmware e-group gitolite-admin GIT repository atlas-lar-ldpb-firmware e-group ATLAS LAr LDPB firmware JIRA project CERN

e-group CERN e-group: atlas-lar-ldpb-firmware ▫ Need to be member of the e-group to be able to access the JIRA and GIT ▫ Request access to e-group owner:  Nicolas Chevillot: ▫ firmware firmware ▫ Current members:  Aad, Georges  Camplani, Alessandra  Chevillot, Nicolas  Dinkespiler, Bernard  Dumont-Dayot, Nicolas  Duval, Pierre-Yves  Enari, Yuji  Hentges, Rainer Guenter  Johns, Kenneth  Starz, Steffen  Tanaka, Junichi  Wingerter, Isabelle  Zhulanov, Vladimir 6

JIRA Project CERN JIRA Project: LDPBFW ▫ ▫ Tasks/Bugs tracking system ▫ Used to plan for tasks, i.e. implement such feature, or improve something ▫ Used to track bugs in the firmware ▫ GIT commits can be linked to JIRA ▫ Simple workflow with 4 state: Open, In progress, Closed and Reopened 7 create issue start progress close issue start progress reopen issue close issue stop progress close issue Open In progress Closed Reopened

JIRA Project CERN JIRA Project: LDPBFW ▫ Issue are classified in components:  env, doc  ABBA: abba-back-all, abba-front-all (need maybe to split into multiple components)  LATOME: latome-doc, latome-fpga, latome-ipctrl, latome-istage, latome-lli, latome-mon, latome-osum, latome-remap, latome-ttc, latome-user  undecided: in case component is not yet known ▫ Issues are assigned to component owner  Can be reassigned to a particular developer 8

GIT repository CERN GIT repository: atlas-lar-ldpb-firmware ▫ Need to be member of e-group ▫ Web access: ▫ GIT clone: ▫ Tracks different revisions of the firmware ▫ Allows to share code between group members ▫ Restricts access to parts of the firmware (using the CERN gitolite-admin repository) ▫ Contains:  doc: working environment documentation  env: working environment scripts  ABBA, LATOME: current projects .git: GIT specific files .gitignore: GIT list of files that cannot be committed in the repository (i.e. temporary files, …) ▫ Could hold more projects related to LDPB! 9

GIT repository GIT workflow ▫ GIT is using clone, pull, add, commit, push commands ▫ Using a simple no branch workflow. Might need to reconsider this option if complexity increases 10 Local user 2 master CERN Local user 1 clone Feature/Bug correction clone push pull add / commit push

GIT repository GIT commits ▫ Need to identify clearly which JIRA issue and component(s) the commit applies to ▫ Commit header should follow the convention:  LDPBFW- ( )  Example: LDPBFW-15 (env, LATOME-ipctrl) Missed asynchronous reset. ▫ As much as possible each commit should be linked to a JIRA issue 11

GIT repository Access rights ▫ Each folder’s access rights are handled in the CERN gitolite-admin repository ▫ Request to e-group owner to update access rights:  Nicolas Chevillot: ▫

GIT repository Tools ▫ GIT can be used either on Windows through Cygwin or in linux environment ▫ Command line tool or GUI, i.e. Tortoise GIT (Windows) 13

Simulation and compilation environment Environment based on makefile/python/TCL scripts ▫ Based on hdl-make (CERN Open Hardware): ▫ Handle dependencies to minimize compile time ▫ Concept of modules, can be used to batch build projects (i.e. testbenches) for regression testing ▫ Supports Cygwin ≥ v (Windows) or Linux environment (tested on SciLinux v6.1):  Git ≥ v2.1.1  Make ≥ v4.1  Python ≥ v2.7.8 ▫ Strongly recommends using Linux based environment (much faster) Note: the structure of the environment is inspired from LHCb project. Work from Guillaume Vouters and others. Simulation environment ▫ Based on Modelsim/Questa tool ≥ v10.2c ▫ Dependencies are built automatically ▫ Faster rebuild ▫ Optional GUI, can be used to remotely build project on faster machine Synthesis environment ▫ Based on Quartus II ≥ v13.1. ABBA using v13.1, LATOME using v15.0. ▫ Optional GUI, can be used to remotely build project on faster machine 14

Simulation and compilation environment 15 Each project holds multiple sub-projects ▫ A sub-project is a simulation testbench, design to be compiled or a design unit ▫ Described using a python file: Manifest.py # Simulating the design action = "simulation" # Simulation tool is Modelsim v10.2c sim_tool = "modelsim" #sim_tool_version = "10.2c" # Compilation tool is Quartus v14.1, used in simulation for Altera primitives #comp_tool = "quartus" #comp_tool_version = "14.1" # Top module used for simulation top_module = "fpga_tb.fpga_tb(struct)" # Waveforms for simulation sim_do_cmd = "wave.do" # Additional options for modelsim vcom_opt = "" vsim_opt = "-voptargs=+acc -i -multisource_delay latest -t ps +typdelays" # List of modules modules = { "local" : [ "$PROJECT_ROOT_PATH/src/fpga", "$PROJECT_ROOT_PATH/src/testbench", ], } # Default library library = "fpga_tb" # List of source files for the 'fpga' module testbench files = [ "fpga_tb.vhd", ]

Simulation and compilation environment 16 Top-level interfaces are described in a python file: top_level.py ▫ Interfaces are either:  Signals  Altera Avalon Streaming (Avalon ST) or Avalon Memory Mapped (Avalon MM)  Custom interfaces (combination of Altera Avalon ST/MM and or signals) ▫ Python file used to automatically generate:  Documentation, i.e. interfaces tables for LAr-LATOME-FW  LATOME-FW.pdf LATOME-FW.pdf  VHDL Code skeleton for each modules, including testbench  VHDL code skeleton documented using doxygen comments

Simulation flow 17 Source files (.vhd,.v, …) Configuration files (manifests, makefile) Relations makefile and manifests VHDL/Verilog Parser Makefile generator Simulation makefile VHDL/Verilog compiler Compiled Libraries Modelsim simulator Modelsim Build environment Input files Environment targets: ▫ clean, relations, generating libraries, simulation

Environment targets: ▫ clean, quartus_project, quartus_gui,..., compilation Compilation flow 18 Source files (.vhd,.v,.tcl, …) Configuration files (manifests, makefile) Makefile generator Compilation makefile Synthesis Compiled FPGA Quartus Build environment Input files

Synthesis flow 19 Synthesis of ABBA_PH0 project: (time in minutes)