Performed by: Jenia Kuksin & Alexander Milys Instructor: Mr. Yossi Hipsh המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Subject: Ultra High Speed Signal Card סמסטר חורף

Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 High Speed Transmission Line Board which will provide an ideal vehicle for learning about Signal Integrity issues like: Reflections in Transmission Lines Cross Talk in Transmission Lines Jitter Skew

System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Instructor Student Controller Switching System Transmission Lines Array

Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware creates short (0.5-1 nsec) and long (10-13 nsec) pulse signal with very low rise/fall time (200ps).Pulser - creates short (0.5-1 nsec) and long (10-13 nsec) pulse signal with very low rise/fall time (200ps). Signal Splitter – launching a signal into a transmission line and converts differential signal to single ended while only one line can be alive at the same time Analog Switches – transmit the measured voltage signal on input/output of selected transmission line to oscilloscope. Transmission Lines – will contain 36 microstrip, single ended transmission lines with different terminations. Based on Altera DE2 Board, controls all of the operation of the High Speed Transmission Line Board.Controller – Based on Altera DE2 Board, controls all of the operation of the High Speed Transmission Line Board. PCB Design  8 layers, 25x30cm board dimensions.  High speed data lines, microstrip and stripline formats.  Rise time of signals range from 150ps to 300ps.  Pre and post layout simulations are required.  Multiple onboard power supplies – many local power planes.  Many identical hierarchical blocks on a schematics require efficient layout reuse.  Design is completed in OrCAD PCB Editor 4

System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Pulser S0 0  narrow pulse 1  wide pulse Signal Splitter S1 Will be OE for splitters Transmission Lines 36 lines Termination Z(Load) Z(Source) Analog Switches Analog Switches S2 Connects One channel from 36 To scope S3 Connects One channel from 36 To scope 36 1 S5 Control for MCP195 (jitter) Controller

Photos המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6