System Demonstrator: status & planning The system demonstrator starts as “vertical slice”: The vertical slice will grow to include all FTK functions, but it will find tracks only in a very small detector tower. After it will grow to cover the barrel → FTK demonstrator (end 2013?) Outline the vertical slice system consumption and cooling tests size of the FTK demonstrator

Where we are: the vertical slice already is born in Bologna. An Atlas crate with the EDRO board and a CDF crate with the old AMBoard (AMB) prototype communicate correctly (2010). Next step: move the AMB in the ATLAS crate, transfer software from CDF, make the system TDAQ compatible, do cooling tests (2011) Bring the system to CERN laboratory: exercise it with TDAQ creating the FTK standard prototype-testing place. All new prototypes coming to CERN will be integrated there (2012) Bring the system to ATLAS: integrate with the experiment, start to parasitically spy data, finally take data & start to grow to cover the barrel (2013). VERTICAL SLICE EVOLUTION: SCHEDULE

3 The importance of EDRO board (Event Dispatch and Read Out, M.Villa) waiting for DF and DO: able to receive data on S-links & feed them to AM: Used in ATLAS as the LUCID DAQ board: –Bunch-by-bunch luminosity evaluation Next use: –ZDC luminosity measurements –Vertical Slice “DO” board Main board + 5 mezzanine structure 9U – VME – 40 MHz board 1 Main Mezzanine with powerfull FPGA –Altera Stratix II 1508 pins 2 Input Mezzanines (EPMC: Edro Programmable Mezzanie Card) 1 Output Mezzanine –S- Link, bandwidth 160 MBytes/s 1 TTCRQ card (clocks, ATLAS trigger handling) THE VERTICAL SLICE - 1 Marco - FTK review

4 SODIMM 256 KB 6 Hit bus out (22 MHz) 1 Track bus out 1 Track bus in (32 MHz) THE VERTICAL SLICE - 2 EDRO V2 Marco - FTK review

5 Vertical Slice plan in Bologna: Bologna (EDRO) - Frascati (pixel clustering ) - Milano-Pavia-Pisa (AMboard). Today MHz Pixel clust. S-links Pixels Fired channels DO Roads+ hits S-link A. Annovi M. Beretta LNF Filar board as interface between SLINK and PC

Amchip-Board-Crate Power consumption corr. Factor Old Chip: 180 nm 1,8 V Core 1,8 Watt New chip 65 nm 1.2 V Core(1.2*1,2)/(1,8*1,8)0,8 Watt Old Chip: Frequency 40 MHz New chip 100 MHz100/402,0 Watt Old Chip: Area 1x1 cm**2 New chip 1,2x1,2 cm**21,44/12,88 Watt New: Pre-match feature1/3 (1/2)0,96 (1,44) Watt Swapping bits 15*8/18*61,07 (1,60) Crate (16 AMB) w old chip 2048 chips/crate 3,7 kW/crate Crate (16 AMB) w new chip 2048 chips/crate 2,18 (3,27) kW/crate IF the pre-match feature save at least 1/3 of current, new 2D chip (0,96 W) ~ 1/2 old chip (1,8 W) ANY OTHER IDEA TO GAIN IN AMCHIP POWER INCREASES THE POTENTIALITY TO GROW IN THE THIRD spatial dimension (3D Amchip) Marco - FTK review

7 Cooling tests with old MHz Each AMchip 1 40 MHz 32 chips/LAMB 128 chips/ AMBoard Board Power consumption: 230 1,8 V today → 128 A today → good test CDF AMB How we provide 128 A to the board? 48V in J1 Each LAMB power connector brings current to half LAMB 16 chips, 8 on each side 1 A/chip, for a total of 16 A V 48 V = 288 W 3.3 cm 2.3 cm DC-DC Converter 48 V→ 1,8 V

The board for the crate test 8 25 A Patio to host DC-DC converters No space for them below the LAMBs 3,5 cm Marco - FTK review

Wiener crate Marco - FTK review U VME 64x Backplane 6023x931 Type Crate (21 slots) VIPA backplane, rear transition cage for 9U card UEL 6020 LX Fan tray with 6 long life DC-fansVHF low-noise switching power supply, Output: 5V/115A, 3.3V/115A, +48V/81A Test 4-5 boards in 40 MHz (fill the crate of boards, even if unused, Z modules). Is heater exchanging with air enough? 0,8 cm Sace lamb – motherboard Amchip was ~ 4 mm thick, Next version will be 1,6 mm thick 6,4 mm left If not, let’s increase the chip-surface contact with air with a thin metal rectangle provided of thermal contact with 8 AMchips

10 Pile-up+WH → AM size# out# out 17.6 evts → 1,7 Mpatterns/region32250/region6150/region FTK demonstrator - Barrel only – end 2013 Average number of roads/processing unit (PU) assuming 1 single PU/region Since our PU can handle up to 8 kroads, we can work with only 1 PU/region To be compared with a PU limit of 8000 output roads. Not large margin, but it is a Demonstrator! From the FTK simulation we find that a very small processor is ok 12 mm^2 Amchip - 6,67 kpatts/chip – 853,7 kpatts/AMBoard 24 mm^2 Amchip - 13,3 kpatts/chip – 1,7 Mpatts/AMBoard With a 24 mm^2 Amchip we need a single PU/region Marco - FTK review

8 PUs /Crate EXS + TF + HW (Final) AM 01 + TSP(DC) + DO + TF + HW EXS + TF + HW (Final) AM 01 + TSP(DC) + DO + TF + HW EXS + TF + HW (Final) AM 01 + TSP(DC) + DO + TF + HW EXS + TF + HW (Final) AM 01 + TSP(DC) + DO + TF + HW VME Controller Extrapolate to SCT stereo + 11-layer fits + removal of 11- layer fit duplicates EXS + TF + HW (Final) AM 01 + TSP(DC) + DO + TF + HW EXS + TF + HW (Final) AM 01 + TSP(DC) + DO + TF + HW EXS + TF + HW (Final) AM 01 + TSP(DC) + DO + TF + HW EXS + TF + HW (Final) AM 01 + TSP(DC) + DO + TF + HW FTK Output tracks 2 links for 8 regions? or each reagion should have its link to L2? If we build the demonstrator with a 24 mm^2 AMchip we need 1 crate for PUs + 2 crates for DFs = 3 crates → 1 rack If we build the demonstrator with a 12 mm^2 Amchip we need 2 crate for PUs + 2 crates for DFs = 4 crates → 2 racks Very compact system! Marco - FTK review

Marco - FTK review Conclusions The Vertical Slice will be the standard test stand for FTK. Cooling tests and prototype tests are expected in TDAQ integration will also be tested with the Vertical Slice The FTK demonstrator will fit into a maximum # of 4 crates Extending FTK to the forward/backward regions we will need 3 boards/region probably up to 2017.